Datasheet

42 NXP Semiconductors
10XS3435
A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during t
OC1
, as shown Figure 18.
Figure 18. Overcurrent profile with OCHI bit set to ‘1’
The wire harness is protected by one of four possible current levels in steady state, as defined in Table 19.
Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 20.
Table 18. Inrush curve selection
OC1_s (D5) OC0_s (D4) Profile curves speed
0 0 slow (default)
0 1 fast
1 0 medium
1 1 very slow
Table 19. Output steady state selection
OCLO1 (D2) OCLO0 (D1) Steady State Current
0 0 OCLO2 (default)
0 1 OCLO3
1 0 OCLO4
1 1 OCLO1
Table 20. Overcurrent mode selection
OC_mode_s (D0) Overcurrent mode
0 only inrush current management (default)
1 inrush current and bulb cooling management
I
OCH
1
I
OCH
2
I
OC1
I
OC
2
I
OC
3
I
OC
4
I
OC
L3
I
OC
L2
I
OC
L1
t
OC1
t
OC2
t
OC3
t
OC4
t
OC5
t
OC6
t
OC7
Time
I
OC
L4