Datasheet

NXP Semiconductors 39
10XS3435
7.4.2.2 Address A
1
A
0
001— Output PWM control register (PWMR_S)
The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is independently
selected for configuration based on the state of the D14
: D13 bits (Table 13).
A logic [1] on bit D8 (28 W_s) selects the 28 W overcurrent protection profile: the overcurrent thresholds are divided by 2 and, the inrush
and cooling responses are dedicated to 28 W lamps for HS[0,1] outputs. This bit it not taken into account for HS[2,3] outputs.
Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also pulled down).
Bits D6:D0 set the output PWM duty-cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 8, page 30.
7.4.2.3 Address A
1
A
0
010— Output configuration register (CONFR0_S)
The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output “s” is independently
selected for configuration based on the state of the D14 : D13 bits (Table 13).
For the selected output, a logic [0] on bit D5 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D5 will disable the output
from direct control (in this case, the output is only controlled by On bit).
D4:D3 bits (SR1_s and SR0_s) are used to select the high or medium or low speed slew rate for the selected output, the default value
[00] corresponds to the medium speed slew rate (Table 14).
Incoming message bits D2 : D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as shown
Table 9, page 30 (only available for PWM_en bit is set to logic [1]).
7.4.2.4 Address A
1
A
0
011 — Output configuration register (CONFR1_S)
The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output “s” is
independently selected for configuration based on the state of the D14
: D13 bits (Table 13).
A logic [1] on bit D6 (RETRY_unlimited_s) disables the autoretry counter for the selected output, the default value [1] corresponds to
enable autoretry feature without time limitation.
A logic [1] on bit D5 (RETRY_dis_s) disables the autoretry for the selected output, the default value [0] corresponds to enable this feature.
A logic [1] on bit D4 (OS_dis_s) disables the output hard shorted to VPWR protection for the selected output, the default value [0]
corresponds to enable this feature.
A logic [1] on bit D3 (OLON_dis_s) disables the ON output openload detection for the selected output, the default value [0] corresponds
to enable this feature (
Table 15).
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF output openload detection for the selected output, the default value [0] corresponds
to enable this feature.
Table 13. Output selection
A
1
(D14) A
0
(D13) HS selection
0 0 HS0 (default)
0 1 HS1
1 0 HS2
1 1 HS3
Table 14. Slew rate speed selection
SR1_s (D4) SR0_s (D3) Slew rate speed
0 0 medium (default)
0 1 low
1 0 high
1 1 Not used