Datasheet

38 NXP Semiconductors
10XS3435
7.4.2 Device register addressing
The following section describes the possible register addresses (D[14:10]) and their impact on device operation.
7.4.2.1 Address XX000 — Status register (STATR_S)
The STATR register is used to read the device status and the various configuration register contents without disrupting the device
operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to the device
status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR and CALR registers
(see
Serial output communication (device status return data).
Table 11. SI message bit assignment
Bit sig SI msg bit Message bit description
MSB D15
Watchdog in: toggled to satisfy watchdog requirements.
D14 : D13
Register address bits used in some cases for output selection (Table 12).
D12 : D10
Register address bits.
D9
Not used (set to logic [0]).
LSB D8:D0
Used to configure the inputs, outputs, and the device protection features and SO status content.
Table 12. Serial input address and configuration bit map
SI Register
SI Data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
STATR_s WDIN X X 0 0 0 0 0 0 0 0 SOA4 SOA3 SOA2 SOA1 SOA0
PWMR_s WDIN
A
1
A
0
0 0 1 0 28W_s ON_s PWM6_s PWM5_s PWM4_s PWM3_s PWM2_s PWM1_s PWM0_s
CONFR0_s WDIN
A
1
A
0
0 1 0 0 0 0 0 DIR_dis_s SR1_s SR0_s DELAY2_s DELAY1_s DELAY0_s
CONFR1_s WDIN
A
1
A
0
0 1 1 0 0 0
Retry_
unlimited_s
Retry_dis_s OS_dis_s OLON_dis_s OLOFF_dis_s OLLED_en_s CSNS_ratio_s
OCR_s WDIN
A
1
A
0
1 0 0 0 Xenon_s BC1_s BC0_s OC1_s OC0_s OCHI_s OLCO1_s OLCO0_s OC_mode_s
GCR WDIN 0 0 1 0 1 0
VDD_FAI
L_en
PWM_en CLOCK_sel TEMP_en CSNS_en CSNS1 CSNS0 X OV_dis
CALR WDIN 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1
Register
state after
RST = 0 or
V
DD(FAIL)
or
V
SUPPLY(POR)
condition
0 0 0 X X X 0 0 0 0 0 0 0 0 0 0
x = Don’t care.
s = Output selection with the bits A
1
A
0
as defined in Table 13.