Datasheet

NXP Semiconductors 37
10XS3435
7.3.7 Ground disconnect protection
In the event the 10XS3435 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless
of the state of the output at the time of disconnection (maximum V
PWR
= 16 V). A 10 kOhm resistor needs to be added between the MCU
and each digital input pin in order to ensure that the device turns off in case of ground disconnect and to prevent this pin from exceeding
maximum ratings.
7.3.8 Loss of supply lines
7.3.8.1 Loss of VDD
If the external VDD supply is disconnected (or not within specification: VDD < VDD
(FAIL)
) with VDD_FAIL_en bit is set to logic [1]), all SPI
register content is reset.
The outputs can still be driven by the direct inputs IN[0 : 3] if V
PWR
is within specified voltage range. The 10XS3435 uses the battery input
to power the output MOSFET-related current sense circuitry and any other internal logic providing Fail-safe device operation with no V
DD
supplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF openload circuitry are fully
operational with default values corresponding to all SPI bits are set to logic [0]. No current is conducted from V
PWR
to V
DD
.
7.3.8.2 Loss of VPWR
If the external VPWR supply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features are
provided for
RST to set to logic [1] under V
DD
in nominal conditions. This fault condition can be diagnosed with UV fault in SPI STATR_s
registers. The SPI pull-up and pull-down current sources are not operational. The previous device configuration is maintained. No current
is conducted from VDD to VPWR.
7.3.8.3 Loss of VPWR and VDD
If the external VPWR and VDD supplies are disconnected (or not within specification: (VDD and VPWR) < V
SUPPLY(POR)
), all SPI register
contents are reset with default values corresponding to all SPI bits are set to logic [0] and all latched faults are also reset.
7.3.9 EMC performances
All following tests are performed on NXP evaluation board in accordance with the typical application schematic.
The device is protected in case of positive and negative transients on the VPWR line (per ISO 7637-2).
The 10XS3435 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level for immunity
tests.
7.4 Logic commands and registers
7.4.1 Serial input communication
SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15 and ending
with the LSB, D0 (
Table 11). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the
MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bits D14 : D13. The next three bits, D12: D10, are
used to select the command register. The remaining nine
bits, D8 : D0, are used to configure and control the outputs and their protection
features.
Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to confirm
transmitted data, as long as the messages are all multiples of 16
bits. Any attempt made to latch in a message that is not 16 bits will be
ignored.
The 10XS3435 has defined registers, which are used to configure the device and to control the state of the outputs. Table 12 summarizes
the SI registers.