Datasheet

32 NXP Semiconductors
10XS3435
7.2.4 Normal and fail-safe mode transitions
7.2.4.1 Transition Fail-safe to Normal mode
To leave the Fail-safe mode, V
DD
must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit set to
logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (autoretry included).
Moreover, the device can be brought out of the Fail-safe mode due to watchdog timeout issue by forcing the FSI pin to logic [0].
7.2.4.2 Transition Normal to Fail-safe mode
To leave the Normal mode, a Fail-safe condition must occurred (fail = 1). The previous latched faults are reset by the transition into Fail-
safe mode (autoretry included).
7.2.5 Fault mode
The 10XS3435 is in Fault mode when:
•V
PWR
and V
DD
are within the normal voltage range,
• Wake-up = 1,
• Fail = X,
• Fault = 1.
This device indicates the faults below as they occur by driving the FS pin to logic [0] for RST input is pulled up:
• Overtemperature fault,
• Overcurrent fault,
• Severe short-circuit fault,
• Output(s) shorted to VPWR fault in OFF state,
• Openload fault in OFF state,
• Overvoltage fault (enabled by default),
• Undervoltage fault.
The FS pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit,
overtemperature and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled).
Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI communication.
The Open load fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x]) and the FS
pin.
7.2.6 Start-up sequence
The 10XS3435 enters in Normal mode after start-up if following sequence is provided:
• VPWR and VDD power supplies must be above their undervoltage thresholds,
• Generate wake-up event (wake-up = 1) from 0 to 1 on RST. The device switches to normal mode with SPI register content is reset
(as defined in
Table 12 and Table 24). All features of the 10XS3435 will be available after 50 μs typical, and all SPI registers are set
to default values (set to logic [0]). The UV fault is reported in the SPI status registers.
• Toggle WD bit from 0 to 1.
And, in case of the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:
• Apply PWM clock on IN0 input pin after maximum 200 μs (min. 50 μs).
If the correct start-up sequence is not provided, the PWM function is not guaranteed.