Datasheet

NXP Semiconductors 31
10XS3435
Figure 13. Internal clock calibration diagram
In case of negative CS pulse is outside a predefined time range (from t
CS(MIN)
to t
CS(MAX)
), the calibration event will be ignored and the
internal clock will be unaltered or reset to default value (f
PWM(0)
) if this was not calibrated before.
The calibratable clock is used, instead of the clock from IN0 input, when CLOCK_sel is set to [1].
7.2.3 Fail-safe mode
The 10XS3435 is in Fail-safe mode when:
•V
PWR
is within the normal voltage range,
• Wake-up = 1,
• Fail = 1,
• Fault = 0.
7.2.3.1 Watchdog
If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or IN_ON[0:3] or RST input pin transitions
from logic
[0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal
clamp current according to the specification.
The watchdog timeout is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), the device will operate normally.
7.2.3.2 Fail-safe conditions
If an internal watchdog time-out occurs before the WD bit for FSI open (Table 10) or in case of V
DD
failure condition (V
DD
< V
DD(FAIL)
) for
VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to logic [1] (see Fail-safe to Normal
mode transition paragraph) and V
DD
is within the normal voltage range.
During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default value
(except POR bit) and fault protections are fully operational.
The Fail-safe mode can be detected by monitoring the NM bit is set to [0].
Table 10. SPI watchdog activation
Typical RFSI (Ohm) Watchdog
0 (shorted to ground) Disabled
(open) Enabled
CS
SI
CALR
SI command
ignored
Internal
clock duration