Datasheet

30 NXP Semiconductors
10XS3435
In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal:
hson[x] = ((IN[x] and DIR_dis[x]) or On bit[x]) and PWM_en) or (On bit [x] and Duty_cycle[x] and PWM_en).
In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below:
fault_control[x] = ((IN_ON[x] and DIR_dis[x]) and PWM_en) or (On bit [x]).
7.2.2.1 Programmable PWM module
The outputs HS[0:3] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1].
The clock frequency from IN0 input pin or from internal clock is the factor 2
7
(128) of the output PWM frequency (CLOCK_sel bit). The
outputs HS[0:3] can be controlled in the range of 5% to 98% with a resolution of 7 bits of duty cycle (Table 8). The state of other IN pin is
ignored.
The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC behavior of
the light module (Table 9).
The clock frequency from IN0 is permanently monitored in order to report a clock failure in case of the frequency is out a specified
frequency range (from f
IN0(LOW)
to f
IN0(HIGH)
). In case of clock failure, no PWM feature is provided, the On bit defines the outputs state and
the CLOCK_fail bit reports [1].
7.2.2.2 Calibratable internal clock
The internal clock can vary as much as +/-30 percent corresponding to typical f
PWM(0)
output switching period.
Using the existing SPI inputs and the precision timing reference already available to the MCU, the 10XS3435 allows clock period setting
within +/-10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration pulse is
provided by the MCU. The pulse is sent on the
CS pin after the SPI word is launched. At the moment, the CS pin transitions from logic [1]
to [0] until from logic [0] to [1] determine the period of internal clock with a multiplicative factor of 128.
Table 8. Output PWM resolution
On bit Duty cycle Output state
0 X OFF
1 0000000 PWM (1/128 duty cycle)
1 0000001 PWM (2/128 duty cycle)
1 0000010 PWM (3/128 duty cycle)
1
n
PWM ((n+1)/128 duty cycle)
1
1111111
fully ON
Table 9. Output PWM switching delay
Delay bits Output delay
000 no delay
001 16 PWM clock periods
010 32 PWM clock periods
011 48 PWM clock periods
100 64 PWM clock periods
101 80 PWM clock periods
110 96 PWM clock periods
111 112 PWM clock periods