Datasheet

26 NXP Semiconductors
10XS3435
6.2.7 Serial clock (SCLK)
The SCLK pin clocks the internal shift registers of the 10XS3435 device. The serial input (SI) pin accepts data into the input shift register
on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge
of the SCLK signal. It is important the SCLK pin be in a logic low state whenever
CS makes any transition. For this reason, it is
recommended the SCLK pin be in a logic
[0] whenever the device is not accessed (CS logic [1] state). SCLK has an active internal pull-
down. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance) (see Figure 10, page 28).
SCLK input has an active internal pull-down, I
DWN
.
6.2.8 Serial input (SI)
This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is
required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 10XS3435 are configured and controlled using
a 5-bit addressing scheme described in
Table 11, page 38. Register addressing and configuration are described in Table 12, page 38. SI
input has an active internal pull-down, I
DWN
.
6.2.9 Digital drain voltage (VDD)
This pin is an external voltage input pin used to supply power to the SPI circuit. In the event V
DD
is lost (V
DD
Failure), the device goes to
Fail-safe mode.
6.2.10 Ground (GND)
These pins are the ground for the device.
6.2.11 Positive power supply (VPWR)
This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside
surface mount tab of the package.
6.2.12 Serial output (SO)
The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into
a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the key inputs, etc. The
SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting descriptions are provided in
Table 24, page 44.
6.2.13 High-side outputs (HS3, HS1, HS0, HS2)
Protected 10 mOhm and 12 mOhm high-side power outputs to the load.
6.2.14 Fail-safe input (FSI)
This pin incorporates an active internal pull-up current source from internal supply (V
REG
). This enables the watchdog time-out feature.
When the FSI pin is opened, the Watchdog circuit is enabled. After a watchdog timeout occurs, the output states depends on IN[0:3].
When the FSI pin is connected to GND, the watchdog circuit is disabled. The output states depends on IN[0:3] in case of VDD Failure
condition, in case VDD failure detection is activated (VDD_FAIL_en bit sets to logic [1]).