Datasheet

24 NXP Semiconductors
10XS3435
Figure 8. SCLK waveform and valid SO data delay time
SO
SO
SCLK
VOH
VOL
VOH
VOL
VOH
VOL
TfSI
TdlyLH
TdlyHL
T
VALID
TrSO
TfSO
3.5V
50%
TrSI
High-to-Low
1.0V
0.7 VDD
0.2VDD
0.2 VDD
0.7 VDD
Low-to-High
t
RSI
t
FSI
90% V
DD
SCLK
SO
SO
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
10% V
DD
10% V
DD
90% V
DD
t
RSO
t
FSO
10% V
DD
t
SO(EN)
t
SO(DIS)
Low to High
High to Low
t
VALID
90% V
DD