Datasheet

22 NXP Semiconductors
10XS3435
5.4 Timing diagrams
Figure 4. Output slew rate and time delays
Figure 5. Overcurrent shutdown protection
V
PWR
V
HS[0:3]
t
DLY(ON)
t
DLY(OFF)
Low logic level
70% V
PWR
30% V
PWR
SR
F
SR
R
50%V
PWR
R
PWM
CS
High logic level
V
HS[0:3]
Time
Time
Time
Low logic level
IN[0:3]
High logic level
Time
or
I
OCH
1
t
OC5
t
OC4
t
OC2
t
OC1
Time
Load
Current
I
OCH2
I
OC1
I
OC3
I
OC4
I
OCLO4
I
OCLO3
I
OC2
t
OC3
t
OC6
t
OC7
I
OCLO2
I
OCLO1