Datasheet

ManualsBrandsNXP ManualsCar video systemsMC12XS3

Document Number: MC10XS3435

Rev. 12.0, 8/2018

NXP Semiconductors

Technical Data

Quad high-side switch

(dual 10 mOhm, dual 35 mOhm)

The 10XS3435 is one in a family of devices designed for low voltage automotive

lighting applications. Its four low R

DS(on)

MOSFETs (dual 10 mOhm/dual

mOhm) can control four separate 55/28 W bulbs, and/or Xenon modules,

and/or LEDs.

Programming, control and diagnostics are accomplished using a 16-bit SPI

interface. Its output with selectable slew rate improves electromagnetic

compatibility (EMC) behavior. Additionally, each output has its own parallel input

or SPI control for pulse-width modulation (PWM) control. The 10XS3435 allows

the user to program via the SPI the fault current trip levels and duration of

acceptable lamp inrush. The device has Fail-safe mode to provide functionality

of the outputs in case of MCU damage. This device is powered using

SMARTMOS technology.

Features

• Four protected 10 mOhm and 35 mOhm high-side switches (at 25 °C)

• Operating voltage range of 6.0 to 20 V with sleep current < 5.0 μA,

extended mode from 4.0 to 28

•8.0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with daisy

chain capability

• PWM module using external clock or calibratable internal oscillator with

programmable outputs delay management

• Smart overcurrent shutdown, severe short-circuit, overtemperature

protections with time limited autoretry, and Fail-safe mode in case of MCU

damage

• Output OFF or ON openload detection compliant to bulbs or LEDs and

short to battery detection

• Analog current feedback with selectable ratio and board temperature

feedback

Figure 1. 10XS3435 simplified application diagram

HIGH-SIDE SWITCH

FK SUFFIX

98ARL10596D

24-PIN PQFN

10XS3435

Applications

• Low-voltage automotive lighting

• Xenon bulbs

• Halogen bulbs

• Light-emitting diodes (LEDs)

• High beam

• Low beam

• Flashers

• Low-voltage industrial lighting

MCU

10XS3435

PWR

WAKE

SCLK

RST

IN0

IN1

IN2

IN3

CSNS

FSI

GND

VDD VPWR

HS0

HS1

HS2

HS3

LOAD

I/O

SCLK

I/O

A/D

GND

LOAD

Summary of content (58 pages)

PAGE 1
NXP Semiconductors Technical Data Document Number: MC10XS3435 Rev. 12.0, 8/2018 Quad high-side switch (dual 10 mOhm, dual 35 mOhm) 10XS3435 The 10XS3435 is one in a family of devices designed for low voltage automotive lighting applications. Its four low RDS(on) MOSFETs (dual 10 mOhm/dual 35 mOhm) can control four separate 55/28 W bulbs, and/or Xenon modules, and/or LEDs. Programming, control and diagnostics are accomplished using a 16-bit SPI interface.
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Table of Contents 1 2 3 4 5 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1 Orderable parts Table 1. Orderable part variations Part number(1) Temperature MC10XS3435BHFK Package - 40 to 125 °C MC10XS3435DHFK 24-pin PQFN Notes 1. To order parts in tape and reel, add the R2 suffix to the part number. 2 Device variations Table 2. Device variations Characteristic Symbol Min Typ Max Unit VCL(WAKE) 18 20 25 27 32 35 V Fault detection blanking time • 10XS3435B • 10XS3435D tFAULT - 5.0 5.
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3 Internal block diagram VDD IUP VPWR Vdd Failure Detection Internal Regulator POR Over/Undervoltage Protections Charge Pump VPWR Voltage Clamp VREG CS SCLK Selectable Slew Rate Gate Driver IDWN Selectable Overcurrent Detection SO SI RST WAKE FS IN0 HS0 Severe Short-circuit Detection Logic Short to VPWR Detection Overtemperature Detection IN1 IN2 Openload Detections IN3 HS0 RDWN IDWN RDWN HS1 Calibratable Oscillator HS1 PWM Module HS2 VREG HS2 HS3 FSI HS3 Programmable Watchd
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4 Pin connections SO 16 GND 17 WAKE FS IN3 IN2 NC IN1 IN0 CSNS 13 12 11 10 RST CS SCLK SI VDD Transparent Top View of Package 9 8 7 6 5 4 3 2 1 14 GND FSI 23 GND 22 18 HS3 24 HS2 15 VPWR 19 20 21 HS1 NC HS0 Figure 3. 10XS3435 pin connections Table 3. 10XS3435 pin definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 25.
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Table 3. 10XS3435 pin definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 25. Pin number Pin name Pin function Formal name 15 VPWR Power Positive power supply 16 SO Output Serial output 18 19 21 22 HS3 HS1 HS0 HS2 Output High-side outputs 4, 20 NC N/A No connect 24 FSI Input Fail-safe input Definition This pin connects to the positive power supply and is the source of operational power for the device.
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5 Electrical characteristics 5.1 Maximum ratings Table 4. Maximum ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ELECTRICAL RATINGS VPWR supply voltage range • Load dump at 25 °C (400 ms) • Maximum operating voltage • Reverse battery VPWR(SS) 41 28 -18 V VDD -0.3 to 5.5 V (7) -0.3 to VDD + 0.3 V WAKE input clamp current ICL(WAKE) 2.
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Table 4. Maximum ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit RθJC RθJA <1.0 30 °C/ W TPPRT Note 10 °C THERMAL RESISTANCE Thermal resistance(8) • Junction to Case • Junction to Ambient Peak Package Reflow Temperature During Reflow(9), (10) Notes 8. Device mounted on a 2s2p test board per JEDEC JESD51-2.
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5.2 Static electrical characteristics Table 5. Static electrical characteristics Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VPWR 6.0 4.0 – – 20 28 V VPWR(CLAMP) 41 47 53 V – 6.5 20 – 6.5 7.5 – – 1.0 – 5.
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Table 5. Static electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max – – – – – – – – 36 16 10 10 – – – – – – – – 62 27 17 17 – – – – 15 20 – – – – – – – – 126 56 35 35 – – – – – – – – 217 94.5 59.5 59.
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Table 5. Static electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max OCHI1_0 78 94.0 110 OCHI2_0 50 60.0 70 OC1_0 44.1 52.5 60.9 OC2_0 37.8 45.0 52.2 OC3_0 31.5 37.5 43.
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Table 5. Static electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max -16 -20 – – 16 20 -5.0 – 5.0 Unit OUTPUTS HS0 TO HS3 (CONTINUED) HS[0,1] current sense ratio (CSR0) accuracy (6.
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Table 5. Static electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max HS[2,3] output overcurrent detection levels (6.0 V < VHS[0:3] < 20 V) OCHI1_1 OCHI2_1 OC1_1 OC2_1 OC3_1 OC4_1 OCLO4_1 OCLO3_1 OCLO2_1 OCLO1_1 39.5 25.2 22.
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Table 5. Static electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Input logic high voltage(23) VIH 2.0 – VDD+0.3 V Input logic low voltage(23) VIL -0.3 – 0.8 V IDWN 5.0 – 20 μA IUP 5.
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5.3 Dynamic electrical characteristics Table 6. Dynamic electrical characteristics Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max 0.15 0.3 0.6 0.07 0.15 0.3 0.3 0.6 1.2 0.15 0.3 0.6 0.07 0.15 0.3 0.3 0.6 1.2 35 60 85 45 70 95 0.8 1.
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Table 6. Dynamic electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Fault detection blanking time(32) • 10XS3435B • 10XS3435D tFAULT - 5.0 5.
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Table 6. Dynamic electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max tOC1_00 4.40 6.30 8.02 tOC2_00 1.62 2.32 3.00 tOC3_00 2.10 3.00 3.90 tOC4_00 2.88 4.12 5.36 tOC5_00 4.58 6.56 8.54 tOC6_00 10.16 14.
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Table 6. Dynamic electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max HS[2,3] output overcurrent time step tOC1_00 3.4 4.9 6.4 OC[1:0] = 00 (slow by default) tOC2_00 1.1 1.6 2.1 tOC3_00 1.4 2.1 2.8 tOC4_00 2.
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Table 6. Dynamic electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
PAGE 20
Table 6. Dynamic electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit fIN0 7.68 – 30.72 kHz fIN0(LOW) 1.0 2.0 4.0 kHz fIN0(HIGH) 100 – 400 kHz fPWM – – 1.
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Table 6. Dynamic electrical characteristics (continued) Characteristics noted under conditions 6.0 V ≤ VPWR ≤ 20 V, 3.0 V ≤ VDD ≤ 5.5 V, - 40 °C ≤ TA ≤ 125 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit f SPI – – 8.0 MHz t WRST 10 – – μs t CS – – 1.0 μs t ENBL – – 5.
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5.4 Timing diagrams IN[0:3] High logic level Low logic level Time or CS High logic level Low logic level Time VHS[0:3] VPWR RPWM 50%VPWR Time t DLY(ON) VHS[0:3] 70% VPWR t DLY(OFF) SR F SR R 30% VPWR Time Figure 4. Output slew rate and time delays IOCH1 IOCH2 Load Current IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 Time t OC1 t OC2 t OC3 t OC4 t OC5 t OC6 t OC7 Figure 5.
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IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t BC3 tB C1 t BC2 t BC4 tB C5 Previous OFF duration (toff) tB C6 Figure 6. Bulb cooling management VIH VIH RSTB RST 10% 0.2 VDDVDD tWRST TwRSTB tENBL VIL VIL tTCSB CS TENBL VIH VIH 90% VDD 0.7VDD CS CSB 10% VDD 0.7VDD t WSCLKH TwSCLKh tTlead LEAD VIL VIL t RSI TrSI t LAG Tlag 90% VDD 0.7VDD SCLK SCLK VIH VIH 10% VDD 0.2VDD t TSIsu SI(SU) VIL VIL t WSCLKl TwSCLKl t SI(HOLD) TSI(hold) SI SI Don’t Care 90% VDD 0.
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tFSI tRSI TrSI TfSI VOH VOH 90% VDD 3.5V 50% SCLK SCLK 1.0V VDD 10% VOL VOL t SO(EN) TdlyLH SO SO 90% VDD 0.7 VDD 0.210% VDDVDD Low-to-High Low to High TrSO t RSO VOH VOH VOL VOL VALID tTVALID SO TfSO t FSO SO VOH VOH VDD VDD High to Low 0.790% High-to-Low 0.2VDD 10% VDD TdlyHL VOL VOL t SO(DIS) Figure 8.
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6 Functional description 6.1 Introduction The 10XS3435 is one in a family of devices designed for low-voltage automotive lighting applications. Its four low RDS(on) MOSFETs (dual 10 mOhm, dual 35 mOhm) can control four separate 55 W/28 W bulbs and/or Xenon modules. Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate improves electromagnetic compatibility (EMC) behavior.
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6.2.7 Serial clock (SCLK) The SCLK pin clocks the internal shift registers of the 10XS3435 device. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CS makes any transition.
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6.3 Functional internal block description MC10XS3435 - Functional Block Diagram Power Supply MCU Interface & Output Control Self-protected High-side Switches HS0-HS3 SPI Interface Parallel Control Inputs MCU Interface PWM Controller Supply MCU Interface & Output Control Self-protected High-side Switches Figure 9. Functional block diagram 6.3.1 Power supply The 10XS3435 is designed to operate from 4.0 to 28 V on the VPWR pin. Characteristics are provided from 6.0 to 20 V for the device.
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7 Functional device operation 7.1 SPI protocol description The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CS). The SI / SO pins of the 10XS3435 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V or 3.3 V CMOS logic levels.
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Table 7. 10XS3435 operating modes Mode wake-up fail fault Sleep 0 x x Device is in Sleep mode. All outputs are OFF. Comments Normal 1 0 0 Device is currently in Normal mode. Watchdog is active if enabled. Fail-Safe 1 1 0 Device is currently in Fail-safe mode due to Watchdog time-out or VDD Failure conditions. The output states are defined with the RFS resistor connected to FSI. Fault 1 X 1 Device is currently in fault mode. The faulted output(s) is (are) OFF.
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In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:3] are under control, as defined by hson signal: hson[x] = ((IN[x] and DIR_dis[x]) or On bit[x]) and PWM_en) or (On bit [x] and Duty_cycle[x] and PWM_en). In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below: fault_control[x] = ((IN_ON[x] and DIR_dis[x]) and PWM_en) or (On bit [x]). 7.2.2.
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CS SI CALR SI command ignored Internal clock duration Figure 13. Internal clock calibration diagram In case of negative CS pulse is outside a predefined time range (from tCS(MIN) to t CS(MAX)), the calibration event will be ignored and the internal clock will be unaltered or reset to default value (fPWM(0)) if this was not calibrated before. The calibratable clock is used, instead of the clock from IN0 input, when CLOCK_sel is set to [1]. 7.2.
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7.2.4 7.2.4.1 Normal and fail-safe mode transitions Transition Fail-safe to Normal mode To leave the Fail-safe mode, VDD must be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit set to logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (autoretry included). Moreover, the device can be brought out of the Fail-safe mode due to watchdog timeout issue by forcing the FSI pin to logic [0]. 7.2.4.
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7.3 Protection and diagnostic features 7.3.1 Protections 7.3.1.1 Overtemperature fault The 10XS3435 incorporates overtemperature detection and shutdown circuitry for each output structure. Two cases need to be considered when the output temperature is higher than TSD: • If the output command is ON: the corresponding output is latched OFF. FS will be also latched to logic [0].
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Depending on toff depending to toff Over-current thresholds Cooling toff fault_control hson signal hson PWM Figure 15. Bulb cooling principle 7.3.1.3 Severe short-circuit fault The 10XS3435 provides output shutdown in order to protect each output in case of severe short-circuit during of the output switching. If the short-circuit impedance is below RSHORT, the device will latch the output OFF, FS will go to logic [0] and the fault register SC[0:3] bit will be set to [1].
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All latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if: • VDD < VDD(FAIL) with VPWR in nominal voltage range, • VDD and VPWR supplies is below VSUPPLY(POR) voltage value.
PAGE 36
7.3.3.2 Openload faults The 10XS3435 incorporates three dedicated openload detection circuitries on the output to detect in OFF and in ON state. 7.3.3.3 Openload detection In OFF state The OFF output openload fault is detected when the output voltage is higher than VOLD(THRES) pulled up with internal current source (IOLD(OFF)) and reported as a fault condition when the output is disabled (OFF).
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7.3.7 Ground disconnect protection In the event the 10XS3435 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection (maximum VPWR = 16 V). A 10 kOhm resistor needs to be added between the MCU and each digital input pin in order to ensure that the device turns off in case of ground disconnect and to prevent this pin from exceeding maximum ratings. 7.3.8 7.3.8.
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Table 11. SI message bit assignment Bit sig SI msg bit MSB D15 Message bit description Watchdog in: toggled to satisfy watchdog requirements. D14 : D13 Register address bits used in some cases for output selection (Table 12). D12 : D10 Register address bits. Not used (set to logic [0]). D9 LSB Used to configure the inputs, outputs, and the device protection features and SO status content. D8:D0 Table 12.
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7.4.2.2 Address A1A0001— Output PWM control register (PWMR_S) The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is independently selected for configuration based on the state of the D14 : D13 bits (Table 13). Table 13.
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A logic [1] on bit D1 (OLLED_en_s) enables the ON output openload detection for LEDs for the selected output, the default value [0] corresponds to ON output openload detection is set for bulbs (Table 15). Table 15. ON openload selection OLON_dis_s (D3) OLLED_en_s (D1) ON OpenLoad detection 0 0 enable with bulb threshold (default) 0 1 enable with LED threshold 1 X disable A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio on the CSNS pin for the corresponding output.
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Xenon bit set to logic [0]: IOCH1 IOCH2 IOC1 IOC2 IOCLO4 IOCLO3 IOCLO2 IOCLO1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 t OC7 Time Xenon bit set to logic [1]: IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOC L4 IOCL3 IOCL2 IOCL1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 t OC7 Time Figure 17. Overcurrent profile depending on Xenon bit D[7:6] bits allow to MCU to programmable bulb cooling curve and D[5:4] bits inrush curve for selected output, as shown Table 17 and Table 18. Table 17.
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Table 18. Inrush curve selection OC1_s (D5) OC0_s (D4) Profile curves speed 0 0 slow (default) 0 1 fast 1 0 medium 1 1 very slow A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during tOC1, as shown Figure 18. IOCH1 IOCH2 IOC1 IOC2 IOC3 IOC4 IOC L4 IOCL3 IOCL2 IOCL1 t OC1 t OC3 t OC4 t OC5 t OC2 t OC6 t OC7 Time Figure 18.
PAGE 43
7.4.2.6 Address 00101 — Global configuration register (GCR) The GCR register allows the MCU to configure the device through the SPI. Bit D8 allows the MCU to enable or disable the VDD failure detector. A logic [1] on VDD_FAIL_en bit allows switch of the outputs HS[0:3] with PWMR register device in Fail-safe mode in case of VDD < VDD(FAIL). Bit D7 allows the MCU to enable or disable the PWM module.
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SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4, OD3, OD2, OD1, and OD0. The value of the previous bits SOA4 and SOA3 will determine which output the SO information applies to for the registers which are output specific; viz., Fault, PWMR, CONFR0, CONFR1 and OCR registers.
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• • • • • • • SC_s: severe short-circuit fault detection for a selected output, OS_s: output shorted to VPWR fault detection for a selected output, OLOFF_s: openload in OFF state fault detection for a selected output, OLON_s: openload in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output, OV: overvoltage fault detection, UV: undervoltage fault detection POR: power-on reset detection. The FS pin reports all faults.
PAGE 46
7.4.4.9 Previous Address SOA4 : SOA0 = 10111 (DIAGR2) The returned data is the product ID. Bits OD2:OD0 are set to 011 for protected dual 10 mOhm and 35 mOhm high-side switches. 7.4.5 Default device configuration The default device configuration is explained below: • HS output is commanded by corresponding IN input or ON bit through SPI.
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8 Typical applications The following figure shows a typical automotive lighting application (only one vehicle corner) using an external PWM clock from the main MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe condition. It is recommended to locate a 22 nF decoupling capacitor to the module connector.
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9 Packaging 9.1 Soldering information The 10XS3435 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board. The AN2467 provides guidelines for printed circuit board design and assembly. 9.2 Package dimensions For the most current package revision, visit www.nxp.com and perform a keyword search using the 98ARL10596D listed below. Dimensions shown are provided for reference ONLY. FK SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D REV.
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FK SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D REV.
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FK SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D REV.
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FK SUFFIX 24-PIN PQFN NONLEADED PACKAGE 98ARL10596D REV.
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10 10.1 Additional documentation 10XS3435 Thermal addendum (Rev 2.0) 10.1.1 Introduction 24-PIN PQFN This thermal addendum is provided as a supplement to the 10XS3435 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application and packaging information is provided in the data sheet. 10.1.2 Package and thermal considerations This 10XS3435 is a dual die package.
PAGE 53
0.2mm 0.2mm 0.5mm dia. Figure 20. Detail of copper traces under device with thermal vias 114.3mm 76.2mm Figure 21.
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114.3mm 76.2mm SO 16 GND 17 HS3 WAKE FS IN3 IN2 NC IN1 IN0 CSNS 13 12 11 10 RST CS SCLK Transparent Top View SI VDD Figure 22. 2s2p JDEC thermal test board (Red - top layer, Yellow - two buried layers) 9 8 7 6 5 4 3 2 1 14 GND 24 FSI 23 GND 22 18 HS2 15 VPWR MC10XS3435 Pin Connections 24-PIN PQFN (12 x 12) 0.9 mm Pitch 12.0mm 12.0mm Body 19 20 21 HS1 NC HS0 Figure 23.
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10.1.4 Device on thermal test board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness Cu buried traces thickness 0.035mm Outline: 76.2 mm x 114.3 mm board area, including edge connector for thermal testing, 74 mm x 74 mm buried layers area Area A: Cu heat-spreading areas on board surface Ambient Conditions: Natural convection, still air Table 27.
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Thermal Resistance [K/W] 100 10 1 0.1 0.00001 0.001 0.1 10 1000 Time[s] Figure 25. Transient thermal 1 W step response; device on 1s JEDEC standard thermal test board with heat spreading areas 600 Sq. mm Thermal resistance [K/W] 100 10 1 0.1 0.00001 0.001 0.1 10 1000 Time [s] Figure 26.
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11 Revision history Revision 4.0 Date 9/2008 Description of changes • Initial release • • • • Revised wording of VPWR Supply Voltage Range in Maximum Rating Table on page 5. Changed parameters for VPWR and VDD Power on Reset Threshold in Static Electrical Characteristics Table on page 7. Changed Maximum rating for Output Source-to-Drain ON Resistance in Static Electrical Characteristics Table on page 8. Changed Typical rating for HS[0,1] Current Sense Ratio (6.0 V < HS[0:3] < 20 V, CSNS < 5.
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