Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 74 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
[1] C
L
= 10 pF
[2] Characterized on typical samples, not tested in production.
[3] Input hysteresis is relative to the reference input channel and is software programmable.
[4] 100 mV overdrive corresponds to a square wave from 50 mV below the reference (V
IC
) to 50 mV above the reference.
[1] Characterized on typical samples, not tested in production.
t
PD
propagation delay HIGH to LOW; V
DD
= 3.0 V; T
amb
=
105
°C
V
IC
= 0.1 V; 100 mV overdrive input
[1][2][4]
-
150
-ns
V
IC
= 0.1 V; rail-to-rail input
[1][2]
-250- ns
V
IC
= 1.5 V; 100 mV overdrive input
[1][2][4]
-150- ns
V
IC
= 1.5 V; rail-to-rail input
[1][2]
-170- ns
V
IC
= 2.9 V; 100 mV overdrive input
[1][2][4]
-180- ns
V
IC
= 2.9 V; rail-to-rail input
[1][2]
-70 - ns
t
PD
propagation delay LOW to HIGH; V
DD
= 3.0 V; T
amb
=
105 °C
V
IC
= 0.1 V; 100 mV overdrive input
[1][2][4]
-
260
-ns
V
IC
= 0.1 V; rail-to-rail input
[1][2]
-90 - ns
V
IC
= 1.5 V; 100 mV overdrive input
[1][2][4]
-270- ns
V
IC
= 1.5 V; rail-to-rail input
[1][2]
-220- ns
V
IC
= 2.9 V; 100 mV overdrive input
[1][2][4]
-190- ns
V
IC
= 2.9 V; rail-to-rail input
[1][2]
-700- ns
V
hys
hysteresis voltage positive hysteresis; V
DD
= 3.0 V;
V
IC
= 1.5 V; T
amb
= 105 °C; settings:
5 mV
[3]
-6 -
mV
10 mV - 12 - mV
20 mV - 22 - mV
V
hys
hysteresis voltage negative hysteresis; V
DD
= 3.0 V;
V
IC
= 1.5 V; T
amb
= 105 °C; settings:
5 mV
[1][3]
-
7
-mV
10 mV - 13 - mV
20 mV - 23 - mV
R
lad
ladder resistance - - 1 - M
Table 29. Comparator characteristics
…continued
T
amb
=  40  C to +105  C unless noted otherwise; V
DD
= 1.8 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
Table 30. Comparator voltage ladder dynamic characteristics
T
amb
=  40  C to +105  C; V
DD
= 1.8 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
t
s(pu)
power-up settling
time
to 99% of voltage
ladder output value
[1]
-17-s
t
s(sw)
switching settling
time
to 99% of voltage
ladder output value
[1]
-18-s