Datasheet
LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 70 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
13.2 ADC
[1] The input resistance of ADC channel 0 is higher than for all other channels. See Figure 33.
[2] In the ADC TRM register, set VRANGE = 0 (default).
[3] In the ADC TRM register, set VRANGE = 1.
[4] Based on characterization. Not tested in production.
[5] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See Figure 34.
[6] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 34
.
[7] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 34
.
[8] The full-scale error voltage or gain error (E
G
) is the difference between the straight line fitting the actual transfer curve after removing
offset error, and the straight line which fits the ideal transfer curve. See Figure 34
.
[9] T
amb
= 25 C; maximum sampling frequency f
s
= 1.2 Msamples/s and analog input capacitance C
ia
= 26 pF.
[10] Input impedance Z
i
(See Section 13.2.1 “ADC input impedance”) is inversely proportional to the sampling frequency and the total input
capacity including C
ia
and C
io
: Z
i
1 / (f
s
C
i
). See Table 13 for C
io
.
Table 27. 12-bit ADC static characteristics
T
amb
=
40
C to +105
C unless noted otherwise; V
DD
= V
DDA
= 2.4 V to 3.6 V; VREFP = V
DD =
V
DDA
; VREFN = V
SS
.
Symbol Parameter Conditions Min Typ Max Unit
V
IA
analog input voltage 0 - V
DDA
V
V
ref
reference voltage on pin VREFP 2.4 - V
DDA
V
C
ia
analog input capacitance - - 26 pF
f
clk(ADC)
ADC clock frequency
[2]
-- 30MHz
f
s
sampling frequency
[2]
- - 1.2 Msamples/s
E
D
differential linearity error
[5][4]
- 3.0 - LSB
E
L(adj)
integral non-linearity
[6][4]
- 2.0 - LSB
E
O
offset error
[7][4]
- 3.5 - LSB
V
err(fs)
full-scale error voltage
[8][4]
-0.1 -%
Z
i
input impedance f
s
= 1.2 Msamples/s
[1][9][10]
0.1 - - M