Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 68 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
12.9 Wake-up process
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up
from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)
wake-up handler. ISR is located in SRAM.
[3] FRO enabled, all peripherals off. PLL disabled.
[4] WKT disabled. Wake up from deep power-down causes the part to go through entire reset
process. The wake-up time measured is the time between when the RESET
pin is triggered to wake the
device up and when a GPIO output pin is set in the reset handler.
Table 25. Dynamic characteristic: Typical wake-up times from low power modes
V
DD
= 3.3 V;T
amb
=25  C; using FRO (12MHz) as the system clock.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
t
wake
wake-up
time
from sleep mode
[2][3]
-2.4 -s
from deep-sleep mode
[2]
-2.5 -s
from power-down mode
[2]
-50 -s
from deep power-down mode;
WKT disabled; using RESET
pin.
[4]
-250 -s