Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 67 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
12.8 USART interface
The actual USART bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for USART
master synchronous mode is 10 Mbit/s, and the maximum supported bit rate for USART
slave synchronous mode is 10 Mbit/s.
Remark: USART functions can be assigned to all digital pins. The characteristics are valid
for all digital pins except the open-drain pins PIO0_10 and PIO0_11.
Table 24. USART dynamic characteristics
T
amb
=  40  C to 105  C; 1.8 V <= V
DD
<= 3.6 V unless noted otherwise; C
L
= 10 pF; input slew =
10 ns. Simulated parameters sampled at the 30 %/70 % level of the falling or rising edge; values
guaranteed by design.
Symbol Parameter Conditions Min Max Unit
USART master (in synchronous mode)
t
su(D)
data input set-up time 3.0 V <= V
DD
<= 3.6 V 31 - ns
1.8 V <= V
DD
< 3.0 V 42
t
h(D)
data input hold time 0 - ns
t
v(Q)
data output valid time 0 7 ns
USART slave (in synchronous mode)
t
su(D)
data input set-up time 5 - ns
t
h(D)
data input hold time 5 - ns
t
v(Q)
data output valid time 3.0 V <= V
DD
<= 3.6 V 0 35 ns
1.8 V <= V
DD
< 3.0 V 0 46 ns
Fig 32. USART timing
Un_SCLK (CLKPOL = 0)
TXD
RXD
T
cy(clk)
t
su(D)
t
h(D)
t
v(Q)
START BIT0
t
vQ)
Un_SCLK (CLKPOL = 1)
START
BIT0
BIT1
BIT1
aaa-015074