Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 64 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
12.7 SPI interfaces
The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is 30 Mbit/s, and the maximum supported bit rate for SPI slave mode is 1/(2 x 26 ns)
= 19 Mbit/s at 3.0v  VDD  3.6v and 1/(2 x 42 ns) = 12 Mbit/s at 1.8v  VDD < 3.0v.
Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for
all digital pins except the open-drain pins PIO0_10 and PIO0_11.
Table 23. SPI dynamic characteristics
T
amb
=  40  C to 105  C; C
L
= 20 pF; input slew = 1 ns. Simulated parameters sampled at the 30 %
and 70 % level of the rising or falling edge; values guaranteed by design. Delays introduced by the
external trace or external device are not considered.
Symbol Parameter Conditions Min Max Unit
SPI master
t
DS
data set-up time 1.8 V <= V
DD
<= 3.6 V 3 - ns
t
DH
data hold time 1.8 V <= V
DD
<= 3.6 V 0 - ns
t
v(Q)
data output valid time 1.8 V <= V
DD
<= 3.6 V 0 5 ns
SPI slave
t
DS
data set-up time 1.8 V <= V
DD
<= 3.6 V 4 - ns
t
DH
data hold time 1.8 V <= V
DD
<= 3.6 V 1 - ns
t
v(Q)
data output valid time 3.0 V <= V
DD
<= 3.6 V 0 26 ns
1.8 V <= V
DD
< 3.0 V 0 42 ns