Datasheet
LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 48 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
[3] I
DD
measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[4] FRO enabled; system oscillator disabled; system PLL disabled.
[5] BOD disabled.
[6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks disabled in system configuration block.
[7] All oscillators and analog blocks turned off.
[8]
WAKEUP pin pulled HIGH externally.
[9] Tested in production, VDD = 3.6 V.
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Fig 16. Deep-sleep mode: Typical supply current I
DD
versus temperature for different
supply voltages V
DD
DDD
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