Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 43 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless
otherwise noted.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 13
) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] Applies to all 5 V tolerant I/O pins except true open-drain pins PIO0_10 and PIO0_11 and except the 3 V tolerant pin PIO0_6.
[4] Including the voltage on outputs in 3-state mode.
[5] V
DD
present or not present. Compliant with the I
2
C-bus standard. 5.5 V can be applied to this pin when V
DD
is powered down.
[6] V
DD
present or not present.
[7] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated
exposure to elevated voltages at 4.6 V must be less than 10
6
s total over the lifetime of the device. Applying an elevated voltage to the
ADC inputs for a long time affects the reliability of the device and reduces its lifetime.
[8] If the comparator is configured with the common mode input V
IC
= V
DD
, the other comparator input can be up to 0.2 V above or below
V
DD
without affecting the hysteresis range of the comparator function.
[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[12] JEDEC (4.5 in  4 in); still air.
[13] Single layer (4.5 in  3 in); still air.
P
tot(pack)
total power dissipation (per
package)
LQFP64, based on package heat
transfer, not device power
consumption
[12]
-0.66W
LQFP64, based on package heat
transfer, not device power
consumption
[13]
-0.48W
LQFP48, based on package heat
transfer, not device power
consumption
[12]
-0.48W
LQFP48, based on package heat
transfer, not device power
consumption
[13]
-0.34W
HVQFN48, based on package
heat transfer, not device power
consumption
[12]
-1.12W
HVQFN48, based on package
heat transfer, not device power
consumption
[13]
-0.46W
HVQFN33, based on package
heat transfer, not device power
consumption
[12]
-0.98W
HVQFN33, based on package
heat transfer, not device power
consumption
[13]
-0.34W
V
esd
electrostatic discharge voltage human body model; all pins - 2000 V
Table 9. Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol Parameter Conditions Min Max Unit