Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 37 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
The LPC84x can be prevented from entering deep power-down mode by setting a lock bit
in the PMU block. Locking out deep power-down mode enables the application to keep
the watchdog timer or the BOD running at all times.
If the part must wake up from deep power-down mode via the WAKEUP
pin or RESET
pin, do not assign any movable function to this pin and must be externally pulled HIGH
before entering deep power-down mode.
Table 7. Peripheral configuration in reduced power modes
Peripheral Sleep mode Deep-sleep
mode
Power-down
mode
Deep power-down
mode
FRO software configurable on off off
FRO output software configurable off off off
Flash software configurable on off off
BOD software configurable software
configurable
software
configurable
off
PLL software configurable off off off
SysOsc software configurable off off off
WDosc/WWDT software configurable software
configurable
software
configurable
off
Digital peripherals software configurable off off off
WKT/low-power oscillator software configurable software
configurable
software
configurable
software configurable
ADC software configurable off off off
DAC0/1 software configurable off off off
Capacitive Touch software configurable software
configurable
software
configurable
off
Comparator software configurable off off off