Datasheet

Product data sheet Rev. 1.7 — 27 February 2018 36 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller

8.27.5.1 Sleep mode

When sleep mode is entered, the clock to the core is stopped. Resumption from the sleep

mode does not need any special sequence but re-enabling the clock to the Arm core.

In sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during sleep mode and may generate

interrupts to cause the processor to resume execution. sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

8.27.5.2 Deep-sleep mode

In deep-sleep mode, the LPC84x core is in sleep mode and all peripheral clocks and all

clock sources are off except for the FRO and watchdog oscillator or low-power oscillator if

selected. The FRO output is disabled. In addition, all analog blocks are shut down and the

flash is in standby mode. In deep-sleep mode, the application can keep the watchdog

oscillator and the BOD circuit running for self-timed wake-up and BOD protection.

The LPC84x can wake up from deep-sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from Capacitive

Touch, or an interrupt from the USART (if the USART is configured in synchronous slave

mode), the SPI, or the I2C blocks (in slave mode).

Any interrupt used for waking up from deep-sleep mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Deep-sleep mode saves power and allows for short wake-up times.

8.27.5.3 Power-down mode

In power-down mode, the LPC84x is in sleep mode and all peripheral clocks and all clock

sources are off except for watchdog oscillator or low-power oscillator if selected. In

addition, all analog blocks and the flash are shut down. In power-down mode, the

application can keep the watchdog oscillator and the BOD circuit running for self-timed

wake-up and BOD protection.

The LPC84x can wake up from power-down mode via a reset, digital pins selected as

inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from Capacitive

Touch, or an interrupt from the USART (if the USART is configured in synchronous slave

mode), the SPI, or the I2C blocks (in slave mode).

Any interrupt used for waking up from power-down mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

Power-down mode reduces power consumption compared to deep-sleep mode at the

expense of longer wake-up times.

8.27.5.4 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the

WAKEUP pin

and the self-wake-up timer. The LPC84x can wake up from deep power-down mode via

the

WAKEUP pin, RESET pin, or without an external signal by using the time-out of the

self-wake-up timer (see Section 8.22