Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 35 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
8.27.5 Power control
The LPC84x supports the Arm Cortex-M0+ sleep mode. The CPU clock rate may also be
controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering
the CPU clock divider value. This allows a trade-off of power versus processing speed
based on application requirements. In addition, a register is provided for shutting down the
clocks to individual on-chip peripherals, allowing to fine-tune power consumption by
eliminating all dynamic power use in any peripherals that are not required for the
application. Selected peripherals have their own clock divider which provides even better
power control.
Fig 13. LPC84x FRO subsystem
set_fro_frequency() API
Divide by 2
Divide by 8
Divide by 2
fro_oscout
30/24/18 MHz
(default = 24 MHz)
FAIM word0,
low power boot bit
FROOSCCTRL[17]
FRO_DIRECT bit
aaa-027256
fro
0
1
0
1
FRO
Oscillator
fro_div
Table 6. Clocking diagram signal name descriptions
Name Description
sys_osc_clk This is the internal clock that comes from external crystal oscillator through dedicated pins.
frg_clk The output of the Fractional Rate Generator. The FRG and its source selection are shown in Figure 12
“LPC84x clock generation (continued)”.
fro The output of the currently selected on-chip FRO oscillator. See UM11029 User manual.
fro_div The FRO output. This may be either 15 MH, 12 MHz, or 9 MHz. See UM11029 User manual.
main_clk The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source
selection are shown in Figure 11 “
LPC84x clock generation”.
“none” A tied-off source that should be selected to save power when the output of the related multiplexer is not
used.
sys_pll0_clk The output of the System PLL. The System PLL and its source selection are shown in Figure 11 “
LPC84x
clock generation”.
wdt_osc_clk The output of the watchdog oscillator, which has a selectable target frequency. It must also be enabled in
the PDRINCFG0 register. See UM11029 User manual.
xtalin Input of the main oscillator. If used, this is connected to an external crystal and load capacitor.
xtalout Output of the main oscillator. If used, this is connected to an external crystal and load capacitor.
clk_in This is the internal clock that comes from the main CLK_IN pin function. Connect that function to the pin by
selecting it in the IOCON block.
external_clk This is the internal clock that comes from the external crystal oscillator or the CLK_IN pin.