Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 34 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
Fig 12. LPC84x clock generation (continued)
aaa-026591
fro
main_clk
sys_pll0_clk
“none”
FRG0 clock select
FRG0CLKSEL[1:0]
FRG1 clock select
FRG1CLKSEL[1:0]
FRG0DIV,
FRG0MULT
FRG1DIV,
FRG1MULT
00
01
10
11
fro
00
01
10
11
Fractional Rate
Divider 0 (FRG0)
Fractional Rate
Divider 1 (FRG1)
fro
main_clk
frg0clk
frg1clk
SPln clock select
SPInCLKSEL[2:0]
000
001
010
011
fro_div
100
“none”
111
SYSAHBCLKCTRL0[SPln]
One for each SPI (SPI0 through SPI1)
to SPIn
fro
main_clk
frg0clk
frg1clk
I2Cn clock select
I2CnCLKSEL[2:0]
000
001
010
011
fro_div
100
“none”
111
SYSAHBCLKCTRL0[I2Cn]
One for each l2C (I2C0 through I2C3)
to I2Cn
fro
main_clk
frg0clk
frg1clk
UARTn clock select
UARTnCLKSEL[2:0]
000
001
010
011
fro_div
100
“none”
111
SYSAHBCLKCTRL0[UARTn]
One for each UART (UART0 through UART4)
to UARTn
watchdog oscillator
WWDT
FRO oscillator
WKT
main_clk
sys_pll0_clk
“none”