Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 33 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
Fig 11. LPC84x clock generation
aaa-026590
sys_osc_clk
fro
external_clk
wd_osc_clk
fro_div
External clock select
EXTCLKSEL[0]
Main clock select
MAINCLKSEL[1:0]
System
PLL
System PLL
settings
sys_pll0_clk
clk_in
0
00
01
10
(1)
11
main_clk_pre_pll
sys_pll0_clk
“none”
“none”
Main clock PLL select
MAINCLKPLLSEL
IOCONCLKDIV(i)
SYSAHBCLKDIV
SYSAHBCLKCTRL
(one bit per destination)
00
01
10
(1)
11
main_clk
main_clk
Divider
to AHB peripherals, AHB
matrix, memories, etc.
to CPU
fro
external_clk
wdt_osc_clk
fro_div
PLL clock select
SYSPLLCLKSEL[1:0]
00
01
10
(1)
11
1
fro
main_clk
sys_pll0_clk
“none”
SCT clock select
SCTCLKSEL[1:0]
00
01
10
11
peripheral_clk
Divider
pin filter(i)
SCTCLKDIV
SYSAHBCLKCTRL0[SCT]
SCT
Clock Divider
to SCT input 4
CLKOUTDIV
CLKOUT
Divider
fro
sys_pll0_clk
“none”
ADC clock select
ADCCLKSEL[1:0]
00
01
11
ADCCLKDIV
ADC Clock
Divider
to ADC
fro
main_clk
sys_pll0_clk
fro_div
CapTouch clock select
CAPTCLKSEL[2:0]
000
001
010
011
wdt_osc_clk
100
“none”
111
SYSAHBCLKCTRL1[CAPT]
to Cap Touch
fro
(1) : synchronized multiplexer, see register desriptions for details.
main_clk
sys_pll0_clk
external_clk
CLKOUT select
CLKOUTSEL[2:0]
000
001
010
011
wdt_osc_clk
100
“none”
111
CLKOUT
Range select and bypass
SYSOSCCTRL[1:0]
Crystal
oscillator
xtalin
xtalout
sys_osc_clk