Datasheet
LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 30 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
The ADC includes a hardware threshold compare function with zero-crossing detection.
Remark: For best performance, select VREFP and VREFN at the same voltage levels as
V
DD
and V
SS
. When selecting VREFP and VREFN different from VDD and VSS, ensure
that the voltage midpoints are the same:
(VREFP-VREFN)/2 + VREFN = V
DD
/2
8.24.1 Features
• 12-bit successive approximation analog to digital converter.
• 12-bit conversion rate of up to 1.2 MSamples/s.
• Two configurable conversion sequences with independent triggers.
• Optional automatic high/low threshold comparison and zero-crossing detection.
• Power-down mode and low-power operating mode.
• Measurement range VREFN to VREFP (not to exceed V
DD
voltage level).
• Burst conversion mode for single or multiple inputs.
• Hardware calibration mode.
8.25 Digital-to-Analog Converter (DAC)
The DAC supports a resolution of 10 bits. Conversions can be triggered by an external pin
input or an internal timer.
The DAC includes an optional automatic hardware shut-off feature which forces the DAC
output voltage to zero while a HIGH level on the external DAC_SHUTOFF pin is detected.
8.25.1 Features
• 10-bit digital-to-analog converter.
• Supports DMA.
• Internal timer or pin external trigger for staged, jitter-free DAC conversion sequencing.
• Automatic hardware shut-off triggered by an external pin.
8.26 CRC engine
The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
8.26.1 Features
• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x
16
+ x
12
+ x
5
+ 1
– CRC-16: x
16
+ x
15
+ x
2
+ 1
– CRC-32: x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1
• Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
• Programmable seed number setting.