Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 29 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
8.23.1 Features
• Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input
hysteresis.
• Two selectable external voltages (V
DD
or ACMPV
REF
); fully configurable on either
positive or negative input channel.
• Internal voltage reference from band gap selectable on either positive or negative
input channel.
• 32-stage voltage ladder with the internal reference voltage selectable on either the
positive or the negative input channel.
• Voltage ladder source voltage is selectable from an external pin or the main 3.3 V
supply voltage rail.
• Voltage ladder can be separately powered down for applications only requiring the
comparator function.
• Interrupt output is connected to NVIC.
• Comparator level output is connected to output pin ACMP_O.
• One comparator output is internally collected to the ADC trigger input multiplexer.
8.24 Analog-to-Digital Converter (ADC)
The ADC supports a resolution of 12 bit and fast conversion rates of up to
1.2 MSamples/s. Sequences of analog-to-digital conversions can be triggered by multiple
sources. Possible trigger sources are the pin triggers, the SCT output SCT_OUT3, the
analog comparator output, and the Arm TXEV.
Fig 10. Comparator block diagram
4
32
4
A
CMP_I[5:1]
V
DD
ACMPVREF
DACOUT_0
internal
voltage
reference
edge detect
sync
comparator
level ACMP_O,
ADC trigger
comparator
edge NVIC
COMPARATOR ANALOG BLOCK COMPARATOR DIGITAL BLOCK
aaa-027485