Datasheet

Product data sheet Rev. 1.7 — 27 February 2018 27 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller

– Reset timer on match with optional interrupt generation.

– Shadow registers are added for glitch-free PWM output.

• For each timer, up to four external outputs corresponding to match registers with the

following capabilities (the number of match outputs for each timer that are actually

available on device pins can vary by device):

– Set LOW on match.

– Set HIGH on match.

– Toggle on match.

– Do nothing on match.

• Up to two match registers can be used to generate timed DMA requests.

• The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

• Up to four match registers can be configured for PWM operation, allowing up to three

single edged controlled PWM outputs. (The number of match outputs for each timer

that are actually available on device pins can vary by device.)

8.20 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

8.20.1 Features

• 31-bit interrupt timer

• Four channels independently counting down from individually set values

• Bus stall, repeat and one-shot interrupt modes

8.21 Windowed WatchDog Timer (WWDT)

The watchdog timer resets the controller if software fails to service the watchdog timer

periodically within a programmable time window.

8.21.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be

disabled.

• Incorrect feed sequence causes reset or interrupt if enabled.

• Flag to indicate watchdog reset.

• Programmable 24-bit timer with internal prescaler.