Datasheet

Product data sheet Rev. 1.7 — 27 February 2018 26 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller

– The following conditions define an event: a counter match condition, an input (or

output) condition such as a rising or falling edge or level, a combination of match

and/or input/output condition.

– Selected events can limit, halt, start, or stop a counter or change its direction.

– Events trigger state changes, output toggles, interrupts, and DMA transactions.

– Match register 0 can be used as an automatic limit.

– In bidirectional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• State control features:

– A state is defined by events that can happen in the state while the counter is

running.

– A state changes into another state as a result of an event.

– Each event can be assigned to one or more states.

– State variable allows sequencing across multiple counter cycles.

• One SCTimer match output can be selected as ADC hardware trigger input.

8.18.2 SCTimer/PWM input MUX (INPUT MUX)

Each input of the SCTimer/PWM is connected to a programmable multiplexer which

allows to connect one of multiple internal or external sources to the input. The available

sources are the same for each SCTimer/PWM input and can be selected from four pins

configured through the switch matrix, the ADC threshold compare interrupt, the

comparator output, and the Arm core signals Arm_TXEV and DEBUG_HALTED.

8.19 CTIMER

8.19.1 General-purpose 32-bit timers/external event counter

The LPC84x has one general-purpose 32-bit timer/counter.

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture inputs to trap the timer value when

an input signal transitions, optionally generating an interrupt.

8.19.2 Features

• A 32-bit timer/counter with a programmable 32-bit prescaler.

• Counter or timer operation.

• Up to three 32-bit captures can take a snapshot of the timer value when an input

signal transitions. A capture event may also optionally generate an interrupt. The

number of capture inputs for each timer that are actually available on device pins can

vary by device.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

– Stop timer on match with optional interrupt generation.