Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 24 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data, which can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data, which allows very
versatile operation, including “any length” frames.
• One Slave Select input/output with selectable polarity and flexible usage.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
8.16 I
2
C-bus interface (I
2
C0/1/2/3)
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example, an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and
can be controlled by more than one bus master.
The I2C0-bus functions are fixed-pin functions. All other I2C-bus functions for I2C1/2/3
are movable functions and can be assigned through the switch matrix to any pin.
However, only the true open-drain pins provide the electrical characteristics to support the
full I2C-bus specification (see Ref. 3
).
8.16.1 Features
• I2C0 supports Fast-mode Plus with data rates of up to 1 Mbit/s in addition to standard
and fast modes on two true open-drain pins.
• True open-drain pins provide fail-safe operation: When the power to an I
2
C-bus
device is switched off, the SDA and SCL pins connected to the I
2
C0-bus are floating
and do not disturb the bus.
• I2C1/2/3 support standard and fast mode with data rates of up to 400 kbit/s.
• Independent Master, Slave, and Monitor functions.
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I
2
C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I
2
C bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
8.17 Capacitive Touch Interface
The Capacitive Touch interface is designed to handle up to nine capacitive buttons in
different sensor configurations, such as slider, rotary, and button matrix. It operates in
sleep, deep sleep, and power-down modes, allowing very low power performance.