Datasheet

Product data sheet Rev. 1.7 — 27 February 2018 23 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller

8.13.2 DMA trigger input MUX (TRIGMUX)

Each DMA trigger is connected to a programmable multiplexer which connects the trigger

input to one of multiple trigger sources. Each multiplexer supports the same trigger

sources: the ADC sequence interrupts, the SCT DMA request lines, and pin interrupts

PININT0 and PININT1, and the outputs of the DMA triggers 0 and 1 for chaining DMA

triggers.

8.14 USART0/1/2/3/4

All USART functions are movable functions and are assigned to pins through the switch

matrix.

8.14.1 Features

• Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in

synchronous mode for USART functions connected to all digital pins except the

open-drain pins.

• 7, 8, or 9 data bits and 1 or 2 stop bits

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485

possible with software address detection and transceiver direction control.)

• Parity generation and checking: odd, even, or none.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator.

• A fractional rate divider is shared among all UARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Separate data and flow control loopback modes for testing.

• Baud rate clock can also be output in asynchronous mode.

8.15 SPI0/1

All SPI functions are movable functions and are assigned to pins through the switch

matrix.

8.15.1 Features

• Maximum data rates of up to 30 Mbit/s in master mode and up to 18 Mbit/s in slave

mode for SPI functions connected to all digital pins except the open-drain pins.