Datasheet

Product data sheet Rev. 1.7 — 27 February 2018 22 of 97

NXP Semiconductors

LPC84x

32-bit Arm Cortex-M0+ microcontroller

Any digital pin, independently of the function selected through the switch matrix, can be

configured through the SYSCON block as input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are on the IO+

bus for fast single-cycle access.

8.12.1 Features

• Pin interrupts

– Up to eight pins can be selected from all digital pins as edge- or level-sensitive

interrupt requests. Each request creates a separate interrupt in the NVIC.

– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

– Level-sensitive interrupt pins can be HIGH- or LOW-active.

– Pin interrupts can wake up the LPC84x from sleep mode, deep-sleep mode, and

power-down mode.

• Pin interrupt pattern match engine

– Up to eight pins can be selected from all digital pins to contribute to a boolean

expression. The boolean expression consists of specified levels and/or transitions

on various combinations of these pins.

– Each minterm (product term) comprising the specified boolean expression can

generate its own, dedicated interrupt request.

– Any occurrence of a pattern match can be also programmed to generate an RXEV

notification to the Arm CPU. The RXEV signal can be connected to a pin.

– The pattern match engine does not facilitate wake-up.

8.13 DMA controller

The DMA controller can access all memories and the USART, SPI, I

C, DAC, and

Capacitive Touch. DMA transfers can also be triggered by internal events like the ADC

interrupts, the pin interrupts (PININT0 and PININT1), the SCTimer DMA requests, CTimer,

and the DMA trigger outputs.

8.13.1 Features

• Twenty five channels with each channel connected to peripheral request inputs.

• DMA operations can be triggered by on-chip events or by two pin interrupts. Each

DMA channel can select one trigger input from13 sources.

• Priority is user selectable for each channel.

• Continuous priority arbitration.

• Address cache with two entries.

• Efficient use of data bus.

• Supports single transfers up to 1,024 words.

• Address increment options allow packing and/or unpacking data.