Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 19 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
8.7 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight
coupling to the CPU allows for low interrupt latency and efficient processing of late arriving
interrupts.
8.7.1 Features
• Nested Vectored Interrupt Controller is a part of the Arm Cortex-M0+.
• Tightly coupled interrupt controller provides low interrupt latency.
• Controls system exceptions and peripheral interrupts.
• Supports 32 vectored interrupts.
• In the LPC84x, the NVIC supports vectored interrupts for each of the peripherals and
the eight pin interrupts.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation using the Arm exceptions SVCall and PendSV.
• Supports NMI.
8.7.2 Interrupt sources
Each peripheral device has at least one interrupt line connected to the NVIC but can have
several interrupt flags. Individual interrupt flags can also represent more than one interrupt
source.
8.8 System tick timer
The Arm Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to
generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).
8.9 I/O configuration
The IOCON block controls the configuration of the I/O pins. Each digital or mixed
digital/analog pin with the PIO0_n designator (except the true open-drain pins PIO0_10
and PIO0_11) in Tabl e 4
can be configured as follows:
• Enable or disable the weak internal pull-up and pull-down resistors.
• Select a pseudo open-drain mode. The input cannot be pulled up above V
DD
. The
pins are not 5 V tolerant when V
DD
is grounded.
• Program the input glitch filter with different filter constants using one of the IOCON
divided clock signals (IOCONCLKCDIV, see Figure 11 “
LPC84x clock generation”).
You can also bypass the glitch filter.
• Invert the input signal.
• Hysteresis can be enabled or disabled.
• For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard
digital operation, for I2C standard and fast modes, or for I2C Fast mode+.
• The switch matrix setting enables the analog input mode on pins with analog and
digital functions. Enabling the analog mode disconnects the digital functionality.
Remark: The functionality of each I/O pin is flexible and is determined entirely through the
switch matrix. See Section 8.10
for details.