Datasheet

LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 17 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
8. Functional description
8.1 Arm Cortex-M0+ core
The Arm Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a
two-stage pipeline. The core revision is r0p1.
Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two
watchpoints. The Arm Cortex-M0+ core supports a single-cycle I/O enabled port for fast
GPIO access.
The core includes a single-cycle multiplier and a system tick timer.
8.2 On-chip flash program memory
The LPC84x contain up to 64 KB of on-chip flash program memory. The flash memory
supports a 64 Byte page size with page write and erase.
8.3 On-chip SRAM
The LPC84x contain a total of 16KB on-chip static RAM data memory in two separate
SRAM blocks with one combined clock for both SRAM blocks. One 8 KB of SRAM can be
used for MTB.
A bit-band module is added in series with the AHB matrix to allow atomic
read-modify-write operations acting on a single bit.
8.4 FAIM memory
The LPC84x includes the FAIM memory and is used to configure the part at start-up. It is
128/256 bits in size and is used to configure the following:
• Clocks and PMU for low-power start-up.
• Low power boot at 1.5 MHz using FAIM memory.
• Pin configuration including direction and pull- up or pull-down.
• Specification of pins to use for ISP entry for each serial peripheral.
• Select whether SWCLK and SWDIO are enabled on reset.
Remark: The FAIM programming voltage range is 3.0 V  Vdd  3.6 V.
8.5 On-chip ROM
The on-chip ROM contains the bootloader:
• Boot loader.
• Supports Flash In-Application Programming (IAP).
• Supports In-System Programming (ISP) through USART, SPI, and I
2
C.
• On-chip ROM APIs for integer divide.
• FAIM API.
• FRO API.