Datasheet
LPC84x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.7 — 27 February 2018 15 of 97
NXP Semiconductors
LPC84x
32-bit Arm Cortex-M0+ microcontroller
[1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
DD
level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see Section 14.6 “
Pin states in
different power modes”. For termination on unused pins, see Section 14.5 “Termination of unused pins”.
[2] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When
configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. This pin is
active in deep power-down mode and includes a 20 ns glitch filter (active in all power modes). In deep power-down mode, pulling the
WAKEUP pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other purposes, if the
WKT low-power oscillator is enabled for waking up the part from deep power-down mode. See Table 20 “
Dynamic characteristics:
WKTCLKIN pin” for the WKTCLKIN input.
[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes
high-current output driver.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[6] True open-drain pin. I
2
C-bus pins compliant with the I
2
C-bus specification for I
2
C standard mode, I
2
C Fast-mode, and I
2
C Fast-mode
Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output
functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all
functions on this pin.
[7] See Figure 14
for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is
available in deep power-down mode. Use the
WAKEUP pin to reset the chip and wake up from deep power-down mode.
[8] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system
oscillator. When configured for XTALIN and XTALOUT, the digital section of the pin is disabled, and the pin is not 5 V tolerant.
[9] The WKTCLKIN function is enabled in the DPDCTRL register in the PMU. See the LPC84x user manual.
[10] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with
configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is
disabled.
[11] Thermal pad for HVQFN33.
V
SSA
53 41 41 Analog ground.
VREFN 41 31 31 20 - - ADC negative reference voltage.
VREFP 42 32 32 21 - - ADC positive reference voltage. Must be equal or
lower than V
DDA
.
Table 4. Pin description
Symbol
LQFP64
LQFP48
HVQFN48
HVQFN33
Reset
state
[1]
Type Description
Table 5. Movable functions (assign to pins PIO0_0 to PIO0_31, PIO1_0 to PIO1_21 through
switch matrix)
Function name Type Description
Ux_TXD O Transmitter output for USART0 to USART4.
Ux_RXD I Receiver input for USART0 to USART4.
Ux_RTS
O Request To Send output for USART0 to USART4.
Ux_CTS
I Clear To Send input for USART0 to USART4.
Ux_SCLK I/O Serial clock input/output for USART0 to USART4 in synchronous mode.
SPIx_SCK I/O Serial clock for SPI0 and SPI1.
SPIx_MOSI I/O Master Out Slave In for SPI0
and SPI1.
SPIx_MISO I/O Master In Slave Out for SPI0 and SPI1.