Datasheet

ManualsBrandsNXP ManualsDevelopment Boards & KitsLPC845 Breakout Board for LPC84x Family MCUs

1. General description

The LPC84x are an Arm Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU

frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and

16 KB of SRAM.

The peripheral complement of the LPC84x includes a CRC engine, four I

C-bus

interfaces, up to five USARTs, up to two SPI interfaces, Capacitive Touch Interface, one

multi-rate timer, self-wake-up timer, SCTimer/PWM, one general purpose 32-bit

counter/timer, a DMA, one 12-bit ADC, two 10-bit DACs, one analog comparator,

function-configurable I/O ports through a switch matrix, an input pattern match engine,

and up to 54 general-purpose I/O pins.

For additional documentation related to the LPC84x parts, see Section 18

2. Features and benefits

 System:

 Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 30 MHz

with single-cycle multiplier and fast single-cycle I/O port.

 Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 AHB multilayer matrix.

 Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported.

 Micro Trace Buffer (MTB).

 Memory:

 Up to 64 KB on-chip flash programming memory with 64 Byte page write and

erase.

 Fast Initialization Memory (FAIM) allowing the user to configure chip behavior on

power-up.

 Code Read Protection (CRP)

 Up to 16 KB SRAM consisting of two 8 KB contiguous SRAM banks. One 8 KB of

SRAM can be used for MTB.

 Bit-band addressing supported to permit atomic operations to modify a single bit.

 ROM API support:

 Boot loader.

 Supports Flash In-Application Programming (IAP).

LPC84x

32-bit Arm

Cortex

-M0+ microcontroller; up to 64 KB flash

and 16 KB SRAM; FAIM memory; 12-bit ADC; 10-bit DACs;

Comparator; Capacitive Touch Interface

Rev. 1.7 — 27 February 2018 Product data sheet

Summary of content (97 pages)

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LPC84x 32-bit Arm® Cortex®-M0+ microcontroller; up to 64 KB flash and 16 KB SRAM; FAIM memory; 12-bit ADC; 10-bit DACs; Comparator; Capacitive Touch Interface Rev. 1.7 — 27 February 2018 Product data sheet 1. General description The LPC84x are an Arm Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC84x support up to 64 KB of flash memory and 16 KB of SRAM.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller      LPC84x Product data sheet  Supports In-System Programming (ISP) through USART, SPI, and I2C.  FAIM API.  FRO API.  On-chip ROM APIs for integer divide. Digital peripherals:  High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and digital filter.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller       Free Running Oscillator (FRO). This oscillator provides a selectable 18 MHz, 24 MHz, and 30 MHz outputs that can be used as a system clock. Also, these outputs can be divided down to 1.125 MHz, 1.5 MHz, 1.875 MHz, 9 MHz, 12 MHz, and 15 MHz for system clock. The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range of 0 C to 70 C.  Low power boot at 1.5 MHz using FAIM memory.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC845M301JBD64 LQFP64 Plastic low profile quad flat package; 64 leads; body 10 10  1.4 mm SOT314-2 LPC845M301JBD48 LQFP48 Plastic low profile quad flat package; 48 leads; body 7 7  1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 5. Marking NXP Terminal 1 index area n Terminal 1 index area aaa-014382 Fig 1. HVQFN48, HVQFN33 package marking Fig 2. 1 aaa-011231 LQFP64, LQFP48 package marking The LPC84x LQFP64 and LQFP48 packages have the following top-side marking: • First line: LPC84xMy01 – y: 3 or 2 • Second line: xxxxxx • Third line: xxxyywwx[R]x – yyww: Date code with yy = year and ww = week. – xR = Boot code version and device revision.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 6.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 7. Pinning information 49 PIO0_14/ACMP_I3/ADC_2 50 PIO0_29/DACOUT_1 51 PIO0_23/ADC_3/ACMP_I4 52 VDDA 53 VSSA 54 PIO0_30/ACMP_I5 55 PIO0_22/ADC_4 56 PIO1_20 57 PIO0_21/ADC_5 58 PIO0_20/ADC_6 59 PIO1_21 60 PIO0_19/ADC_7 61 PIO0_18/ADC_8 62 PIO1_11 63 PIO0_17/ADC_9/DACOUT_0 64 PIO1_10 7.
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LPC84x NXP Semiconductors 37 PIO0_14/ACMP_I3/ADC_2 38 PIO0_29/DACOUT_1 39 PIO0_23/ADC_3/ACMP_I4 40 VDDA 41 VSSA 42 PIO0_30/ACMP_I5 43 PIO0_22/ADC_4 44 PIO0_21/ADC_5 45 PIO0_20/ADC_6 46 PIO0_19/ADC_7 47 PIO0_18/ADC_8 48 PIO0_17/ADC_9/DACOUT_0 32-bit Arm Cortex-M0+ microcontroller PIO1_8/CAPT_YL 1 36 PIO0_0/ACMP_I1/TDO PIO0_13/ADC_10 2 35 PIO1_7/CAPT_X8 PIO1_9/CAPT_YH 3 34 PIO0_6/ADC_1/ACMPVREF PIO0_12 4 33 PIO0_7/ADC_0 PIO0_5/RESET 5 32 VREFP PIO0_4/ADC_11/TRST/WAKEUP 6 31 VRE
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LPC84x NXP Semiconductors 37 PIO0_14/ADC_2/ACMP_I3 38 PIO0_29/DACOUT_1 39 PIO0_23/ADC_3/ACMP_I4 40 VDDA 41 VSSA 42 PIO0_30/ACMP_I5 43 PIO0_22/ADC_4 44 PIO0_21/ADC_5 45 PIO0_20/ADC_6 46 PIO0_19/ADC_7 terminal 1 index area 47 PIO0_18/ADC_8 48 PIO0_17/ADC_9/DACOUT_0 32-bit Arm Cortex-M0+ microcontroller PIO1_8/CAPT_YL 1 36 PIO0_0/ACMPIN_I1/TDO PIO0_13/ADC_10 2 35 PIO1_7/CAPT_X8 PIO1_9/CAPT_YH 3 34 PIO0_6/ADC_1/ACMPVREF PIO0_12 4 33 PIO0_7/ADC_0 PIO0_5/RESET 5 32 VREFP PIO0_4/ADC_
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LPC84x NXP Semiconductors PIO0_17/ADC_9/DACOUT_0 PIO0_18/ADC_8 PIO0_19/ADC_7 PIO0_20/ADC_6 PIO0_21/ADC_5 PIO0_22/ADC_4 PIO0_23/ADC_3/ACMP_I4 PIO0_14/ACMP_I3/ADC_2 31 30 29 28 27 26 25 terminal 1 index area 32 32-bit Arm Cortex-M0+ microcontroller PIO0_13/ADC_10 1 24 PIO0_0/ACMP_I1/TDO PIO0_12 2 23 PIO0_6/ADC_1/ACMPVREF PIO0_7/ADC_0 PIO0_5/RESET 3 22 PIO0_4/ADC_11/TRST/WAKEUP 4 21 VREFP PIO0_28/WKTCLKIN 5 20 VREFN SWCLK/PIO0_3/TCK 6 SWDIO/PIO0_2/TMS 7 PIO0_11/I2C0_S
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller PIO0_10 and PIO_11 are high current source pins while PIO0_2, PIO0_3, PIO0_12, and PIO0_16 are high drive output pins. The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode. Table 4.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 4. Pin description LQFP48 HVQFN48 HVQFN33 RESET/PIO0_5 LQFP64 Symbol 5 5 5 3 Reset Type Description state[1] [7] I; PU I RESET — External reset input: A LOW-going pulse (minimum 20 ns to maximum 50 ns) on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. This pin triggers a wake-up from deep power-down mode.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 4. Pin description LQFP48 HVQFN48 HVQFN33 PIO0_14/ ACMP_I3/ADC_2 LQFP64 Symbol 49 37 37 25 Reset Type Description state[1] [2] I; PU IO PIO0_14 — General-purpose port 0 input/output 14. A ACMP_I3 — Analog comparator common input 3. A ADC_2 — ADC input 2. PIO0_15 30 22 22 15 [5] I; PU IO PIO0_15 — General-purpose port 0 input/output 15.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 4. Pin description HVQFN48 HVQFN33 PIO0_31/CAPT_X0 13 LQFP48 LQFP64 Symbol 9 9 - Reset Type Description state[1] [5] I; PU IO I; PU IO I; PU IO PIO0_31 — General-purpose port 0 input/output 31. CAPT_X0 — Capacitive Touch X sensor 0. PIO1_0/CAPT_X1 15 11 11 - [5] PIO1_1/CAPT_X2 18 14 14 - [5] I; PU IO I; PU IO PIO1_0 — General-purpose port 1 input/output 0. CAPT_X1 — Capacitive Touch X sensor 1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Pin description LQFP48 HVQFN48 Reset Type Description state[1] LQFP64 Symbol HVQFN33 Table 4. VSSA 53 41 41 VREFN 41 31 31 20 - - ADC negative reference voltage. VREFP 42 32 32 21 - - ADC positive reference voltage. Must be equal or lower than VDDA. Analog ground.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 5. LPC84x Product data sheet Movable functions (assign to pins PIO0_0 to PIO0_31, PIO1_0 to PIO1_21 through switch matrix) Function name Type Description SPIx_SSEL0 I/O Slave select 0 for SPI0 and SPI1. SPIx_SSEL1 I/O Slave select 1 for SPI0 and SPI1. SPIx_SSEL2 I/O Slave select 2 for SPI0 and SPI1. SPIx_SSEL3 I/O Slave select 3 for SPI0 and SPI1. SCT_PIN0 I Pin input 0 to the SCT input multiplexer.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8. Functional description 8.1 Arm Cortex-M0+ core The Arm Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a two-stage pipeline. The core revision is r0p1. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The Arm Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 8.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.6 Memory map The LPC84x incorporates several distinct memory regions. Figure 8 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The Arm private peripheral bus includes the Arm core registers for controlling the NVIC, the system tick timer (SysTick), and the reduced power modes.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.1 Features • • • • • Nested Vectored Interrupt Controller is a part of the Arm Cortex-M0+. Tightly coupled interrupt controller provides low interrupt latency.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.9.1 Standard I/O pad configuration Figure 9 shows the possible pin modes for standard I/O pins with analog input function: • • • • • • Digital output driver with configurable open-drain output. Digital input: Weak pull-up resistor (PMOS device) enabled/disabled. Digital input: Weak pull-down resistor (NMOS device) enabled/disabled. Digital input: Repeater mode enabled/disabled.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.10 Switch Matrix (SWM) The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions, for example, the USART, SPI, SCTimer/PWM, CTimer, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in Table 5.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Any digital pin, independently of the function selected through the switch matrix, can be configured through the SYSCON block as input to the pin interrupt or pattern match engine. The registers that control the pin interrupt or pattern match engine are on the IO+ bus for fast single-cycle access. 8.12.1 Features • Pin interrupts – Up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.13.2 DMA trigger input MUX (TRIGMUX) Each DMA trigger is connected to a programmable multiplexer which connects the trigger input to one of multiple trigger sources. Each multiplexer supports the same trigger sources: the ADC sequence interrupts, the SCT DMA request lines, and pin interrupts PININT0 and PININT1, and the outputs of the DMA triggers 0 and 1 for chaining DMA triggers. 8.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller • Data frames of 1 to 16 bits supported directly. Larger frames supported by software. • Master and slave operation. • Data can be transmitted to a slave without the need to read incoming data, which can be useful while setting up an SPI memory. • Control information can optionally be written along with data, which allows very versatile operation, including “any length” frames.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The Capacitive Touch module measures the change in capacitance of an electrode plate when an earth-ground connected object (for example, finger) is brought within close proximity. 8.18 SCTimer/PWM The SCTimer/PWM can perform basic 16-bit and 32-bit timer/counter functions with match outputs and external and internal capture inputs.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller – The following conditions define an event: a counter match condition, an input (or output) condition such as a rising or falling edge or level, a combination of match and/or input/output condition. – Selected events can limit, halt, start, or stop a counter or change its direction. – Events trigger state changes, output toggles, interrupts, and DMA transactions. – Match register 0 can be used as an automatic limit.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller – Reset timer on match with optional interrupt generation. – Shadow registers are added for glitch-free PWM output. • For each timer, up to four external outputs corresponding to match registers with the following capabilities (the number of match outputs for each timer that are actually available on device pins can vary by device): – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The WatchDog Clock (WDCLK) is generated by the dedicated watchdog oscillator (WDOSC). 8.22 Self-Wake-up Timer (WKT) The self-wake-up timer is a 32-bit, loadable down counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller VDD COMPARATOR ANALOG BLOCK COMPARATOR DIGITAL BLOCK ACMPVREF 4 32 sync comparator level ACMP_O, ADC trigger edge detect comparator edge NVIC DACOUT_0 internal voltage reference ACMP_I[5:1] 4 aaa-027485 Fig 10. Comparator block diagram 8.23.1 Features • Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input hysteresis.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The ADC includes a hardware threshold compare function with zero-crossing detection. Remark: For best performance, select VREFP and VREFN at the same voltage levels as VDD and VSS. When selecting VREFP and VREFN different from VDD and VSS, ensure that the voltage midpoints are the same: (VREFP-VREFN)/2 + VREFN = VDD/2 8.24.1 Features • • • • • • • • 12-bit successive approximation analog to digital converter.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller • Supports CPU PIO or DMA back-to-back transfer. • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle). 8.27 Clocking and power control 8.27.1 Crystal and internal oscillators The LPC84x include four independent oscillators: 1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The internal low-power 10 kHz ( 40% accuracy) oscillator serves as the clock input to the WKT. This oscillator can be configured to run in all low-power modes. 8.27.2 Clock input An external clock source can be supplied on the selected CLKIN pin directly to the PLL input.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller sys_osc_clk clk_in fro SYSAHBCLKCTRL (one bit per destination) 00 0 external_clk 1 wd_osc_clk fro_div 01 main_clk_pre_pll 10 sys_pll0_clk 11 External clock select EXTCLKSEL[0] (1) “none” 01 main_clk main_clk Divider 10 “none” 11 Main clock select MAINCLKSEL[1:0] to AHB peripherals, AHB matrix, memories, etc.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller One for each UART (UART0 through UART4) fro main_clk frg0clk 000 SYSAHBCLKCTRL0[UARTn] 001 to UARTn 010 frg1clk 011 fro_div 100 “none” 111 UARTn clock select UARTnCLKSEL[2:0] fro One for each l2C (I2C0 through I2C3) 00 main_clk sys_pll0_clk “none” 01 10 Fractional Rate Divider 0 (FRG0) fro main_clk 11 FRG0 clock select FRG0CLKSEL[1:0] FRG0DIV, FRG0MULT frg0clk 000 SYSAHBCLKCTRL0[I2Cn] 001 to I2Cn 010 frg1clk 011
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Divide by 2 0 Divide by 8 1 FAIM word0, low power boot bit 0 fro FRO Oscillator fro_oscout 1 30/24/18 MHz (default = 24 MHz) FROOSCCTRL[17] FRO_DIRECT bit set_fro_frequency() API Divide by 2 fro_div aaa-027256 Fig 13. LPC84x FRO subsystem Table 6. Clocking diagram signal name descriptions Name Description sys_osc_clk This is the internal clock that comes from external crystal oscillator through dedicated pins.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.27.5.1 Sleep mode When sleep mode is entered, the clock to the core is stopped. Resumption from the sleep mode does not need any special sequence but re-enabling the clock to the Arm core. In sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during sleep mode and may generate interrupts to cause the processor to resume execution.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The LPC84x can be prevented from entering deep power-down mode by setting a lock bit in the PMU block. Locking out deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times. If the part must wake up from deep power-down mode via the WAKEUP pin or RESET pin, do not assign any movable function to this pin and must be externally pulled HIGH before entering deep power-down mode. Table 7.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 8. Wake-up sources for reduced power modes power mode Sleep Deep-sleep and power-down Wake-up source Conditions Any interrupt Enable interrupt in NVIC. RESET pin PIO0_5 Enable the reset function in the PINENABLE0 register via switch matrix. Pin interrupts Enable pin interrupts in NVIC and STARTERP0 registers.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.28 System control 8.28.1 Reset Reset has four sources on the LPC84x: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the FRO and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.28.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8.29 Emulation and debugging Debug functions are integrated into the Arm Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The Arm Cortex-M0+ is configured to support up to four breakpoints and two watch points. The Micro Trace Buffer is implemented on the LPC84x. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the Arm SWD debug (RESET = HIGH).
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions [2] VDD supply voltage (core and external rail) VDDA Analog supply voltage on pin VDDA Vref reference voltage on pin VREFP input voltage 5 V tolerant I/O pins; VDD  1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 9. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Ptot(pack) Vesd [1] Parameter Conditions total power dissipation (per package) electrostatic discharge voltage Min Max Unit LQFP64, based on package heat transfer, not device power consumption [12] - 0.66 W LQFP64, based on package heat transfer, not device power consumption [13] - 0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11. Static characteristics 11.1 General operating conditions Table 11. General operating conditions Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit fclk clock frequency internal CPU/system clock - - 30 MHz 1.8 - 3.6 V 3.0 - 3.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11.2 Power-up ramp conditions Table 12. Power-up characteristics[1] Tamb = 40 C to +105 C. Symbol Parameter Min Typ Max Unit twd Window duration - - 8 ms (time where V1 1.8 V if the power-up characteristic specification cannot be implemented.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11.3 Power consumption Power measurements in active, sleep, deep-sleep, and power-down modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW. Table 13. Static characteristics, supply pins Tamb = 40 C to +105 C, unless otherwise specified.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller [3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [4] FRO enabled; system oscillator disabled; system PLL disabled. [5] BOD disabled. [6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks disabled in system configuration block. [7] All oscillators and analog blocks turned off. [8] WAKEUP pin pulled HIGH externally.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller DDD ,'' $ 9 9 9 WHPSHUDWXUH & Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 17.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller DDD ,'' $ 9 9 9 9 WHPSHUDWXUH & WKT running with internal 10 kHz low-power oscillator. Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD (internal clock) DDD ,'' $ 9 9 9 9 WHPSHUDWXUH & WKT running with external 10 kHz clock.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller DDD ,'' $ 9 9 9 9 WHPSHUDWXUH & WKT running with external 32 kHz clock. Clock input waveform: square wave with rise time and fall time of 5 ns. Fig 21.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11.4 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code accessing the peripheral is executed. Measured on a typical sample at Tamb = 25 C.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 14. Power consumption for individual analog and digital blocks …continued Peripheral Typical supply current in μA Notes System clock frequency = n/a 12 MHz 30 MHz USART3 - 58 142 - USART4 - 56 137 - Comparator ACMP - 79 144 - ADC - 78 190 Digital controller only. Analog portion of the ADC disabled in the PDRUNCFG register. - 78 190 Combined analog and digital logic.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11.5 Pin characteristics Table 15. Static characteristics, pin characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins configured as digital pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10[2] nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 15. Static characteristics, pin characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10[2] VI input voltage VDD  1.8 V 0 - 5.0 V VDD = 0 V 0 - 3.6 V output active VO output voltage 0 - VDD V VIH HIGH-level input voltage 0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 15. Static characteristics, pin characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol ILI Parameter Conditions input leakage current [7] VI = VDD VI = 5 V Min Typ[1] Max Unit - 2 4 A - 10 22 A [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [2] Based on characterization. Not tested in production.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11.5.1 Electrical pin characteristics DDD 92+ 9 DDD 92+ 9 & & & & & & & & ,2+ P$ Conditions: VDD = 1.8 V; on pin PIO0_12. ,2+ P$ Conditions: VDD = 3.3 V; on pin PIO0_12. Fig 23.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller DDD ,2/ P$ DDD ,2/ P$ & & & & & & & & 92/ 9 Conditions: VDD = 1.8 V; standard port pins and high-drive pin PIO0_12. 92/ 9 Conditions: VDD = 3.3 V; standard port pins and high-drive pin PIO0_12. Fig 25.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller DDD ,SX $ DDD ,SX $ & & & & & & & & 9, 9 Conditions: VDD = 1.8 V; standard port pins. 9, 9 Conditions: VDD = 3.3 V; standard port pins. Fig 27.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12. Dynamic characteristics 12.1 Flash memory Table 16. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 18. Dynamic characteristics: Watchdog oscillator Symbol Parameter Conditions fosc(int) internal oscillator frequency DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register Min Typ[1] Max Unit [2][3] - 9.4 - kHz [2][3] - 2300 - kHz [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12.6 I2C-bus Table 22. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C; values guaranteed by design.[2] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz Fast-mode 0 400 kHz Fast-mode Plus; on pins PIO0_10 and PIO0_11 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12.7 SPI interfaces The actual SPI bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for SPI master mode is 30 Mbit/s, and the maximum supported bit rate for SPI slave mode is 1/(2 x 26 ns) = 19 Mbit/s at 3.0v  VDD  3.6v and 1/(2 x 42 ns) = 12 Mbit/s at 1.8v  VDD < 3.0v.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MOSI (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MOSI (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MISO (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MISO (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VALID
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) SSEL MISO (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MISO (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB) tDH tDS MOSI (CPHA = 0) DATA VALID (LSB) DATA VALID tv(Q) tv(Q) DATA VALID (LSB) DATA VALID tDS MOSI (CPHA = 1) DATA VALID (LSB) DATA VALID (MSB) IDLE DATA VALID (MSB) DATA VALID (MSB) IDLE DATA VALID (MSB) tDH DATA VALID
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12.8 USART interface The actual USART bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. Excluding delays introduced by external device and PCB, the maximum supported bit rate for USART master synchronous mode is 10 Mbit/s, and the maximum supported bit rate for USART slave synchronous mode is 10 Mbit/s.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12.9 Wake-up process Table 25. Dynamic characteristic: Typical wake-up times from low power modes VDD = 3.3 V;Tamb = 25 C; using FRO (12MHz) as the system clock. Symbol Parameter twake wake-up time Min Typ[1] Max Unit [2][3] - 2.4 - s from deep-sleep mode [2] - 2.5 - s from power-down mode [2] - 50 - s from deep power-down mode; WKT disabled; using RESET pin.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 13. Characteristics of analog peripherals 13.1 BOD Table 26. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 1 Min Typ Max Unit assertion - 2.25 - V de-assertion - 2.38 - V assertion - 2.55 - V de-assertion - 2.66 - V interrupt level 2 interrupt level 3 assertion - 2.84 - V de-assertion - 2.92 - V assertion - 1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 13.2 ADC Table 27. 12-bit ADC static characteristics Tamb = 40 C to +105 C unless noted otherwise; VDD = VDDA = 2.4 V to 3.6 V; VREFP = VDD = VDDA; VREFN = VSS. Symbol Parameter VIA analog input voltage Vref reference voltage Cia analog input capacitance Conditions Min 0 on pin VREFP 2.4 Typ Max Unit - VDDA V - VDDA V - - 26 pF ADC clock frequency [2] - - 30 MHz fs sampling frequency [2] - - 1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller offset error EO gain error EG 4095 4094 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 offset error EO 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (LSBideal) 1 LSB = VREFP - VREFN 4096 aaa-016908 Fig 33. 12-bit ADC characteristics LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 13.2.1 ADC input impedance Figure 34 shows the ADC input impedance. In this figure: • • • • ADCx represents ADC input channel 0. ADCy represents ADC input channels 1 to 11. R1 and Rsw are the switch-on resistance on the ADC input channel. If ADC input channel 0 is selected, the ADC input signal goes through R1 + Rsw to the sampling capacitor (Cia).
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 13.3 Comparator and internal voltage reference Table 28. Internal voltage reference static and dynamic characteristics Tamb = 40 C to +105 C; VDD = 3.3 V; hysteresis disabled in the comparator CTRL register. Symbol Parameter VO output voltage Conditions Min Tamb = 25 C to 105C 860 Tamb = 25 C Typ Max Unit - 940 mV 904 mV aaa-014424 0.910 VO ref (mV) (V) 0.905 0.900 0.895 0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 29. Comparator characteristics …continued Tamb = 40 C to +105 C unless noted otherwise; VDD = 1.8 V to 3.6 V. Symbol Parameter Conditions tPD propagation delay HIGH to LOW; VDD = 3.0 V; Tamb = 105 °C propagation delay tPD Vhys hysteresis voltage Min Typ Max Unit - ns 150 VIC = 0.1 V; 100 mV overdrive input [1][2][4] - VIC = 0.1 V; rail-to-rail input [1][2] - 250 - ns VIC = 1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 31. Comparator voltage ladder reference static characteristics VDD = 1.8 V to 3.6 V. Tamb = -40 C to + 105C; external or internal reference.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 14. Application information 14.1 Start-up behavior Figure 36 shows the start-up timing after reset. The FRO 12 MHz oscillator provides the default clock at Reset and provides a clean system clock shortly after the supply pins reach operating voltage. FRO starts FRO status internal reset VDD valid threshold = 1.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 14.2 XTAL oscillator In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2 need to be connected externally on XTALIN and XTALOUT. See Figure 37. LPCxxxx L XTALIN XTALOUT = CL CP XTAL RS CX1 CX2 aaa-025725 Fig 37. XTAL oscillator components For best results, it is very critical to select a matching crystal for the on-chip oscillator.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 14.2.1 XTAL Printed Circuit Board (PCB) design guidelines • Connect the crystal and external load capacitors on the PCB as close as possible to the oscillator input and output pins of the chip. • The length of traces in the oscillation circuit should be as short as possible and must not cross other signal lines. • Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal usage, have a common ground plane.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 3.3 V 3.3 V SWD connector (4) 1 ~10 kΩ - 100 kΩ (6) SWDIO/PIO0_2 2 3.3 V ~10 kΩ - 100 kΩ 3 SWCLK/PIO0_3 4 PIO0_8/XTALIN (6) n.c. 5 6 n.c. 7 8 n.c. 9 10 C1 Note 1 C2 PIO0_9/XTALOUT DGND RESETN/PIO0_5 VSS DGND DGND Note 2 VDD 3.3 V LPC84x 0.1 μF PIO0_12 0.01 μF DGND ISP select pin PIO0_6/ADC_1/ACMPVREF Note 5 (ADC_1), Note 3 (ACMPVREF) Note 5 ADC_0 Note 3 VREFP 3.3 V 0.1 μF 0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 14.4 I/O power consumption I/O pins are contributing to the overall dynamic and static power consumption of the part. If pins are configured as digital inputs, a static current can flow depending on the voltage level at the pin and the setting of the internal pull-up and pull-down resistors. This current can be calculated using the parameters Rpu and Rpd given in Table 15 for a given input voltage VI.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 14.6 Pin states in different power modes Table 35. Pin states in different power modes Pin Active Sleep Deep-sleep/powerdown PIOn_m pins (not As configured in the IOCON[1]. Default: internal pull-up I2C) enabled. Deep power-down Floating. Open-drain I2C-bus pins As configured in the IOCON[1]. Floating. RESET Reset function enabled. Default: input, internal pull-up enabled.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 15. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 wM θ bp pin 1 index 64 Lp L 17 detail X 16 1 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm D B A terminal 1 index area A A1 E c detail X C e1 e 9 y1 C C A B C v w 1/2 e b y 16 L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 25 X Dh 0 2.5 Dimensions (mm are the original dimensions) Unit(1) mm A(1) A1 b max 0.05 0.30 nom 0.85 min 0.00 0.18 c D(1) Dh E(1) Eh 5.1 3.75 5.1 3.75 0.2 4.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm D B SOT619-1 A terminal 1 index area A A1 E c detail X C e1 e 1/2 e b 13 24 L y y1 C C A B C v w 25 12 e e2 Eh 1/2 e 1 36 terminal 1 index area 48 37 Dh X 0 2.5 5 mm scale Dimensions (mm are the original dimensions) Unit(1) mm A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 16. Soldering Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D1 D2 (8×) Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 44.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Footprint information for reflow soldering of LQFP64 package SOT314-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 13.300 13.300 10.300 10.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 10.500 10.500 13.550 13.550 sot314-2_fr Fig 45.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Fig 46. Reflow soldering of the HVQFN48 package (7x7) 1 of 3 LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.7 — 27 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Fig 47. Reflow soldering of the HVQFN48 package (7x7) 2 of 3 LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.7 — 27 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Fig 48. Reflow soldering of the HVQFN48 package (7x7) 3 of 3 LPC84x Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.7 — 27 February 2018 © NXP Semiconductors N.V. 2018. All rights reserved.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Footprint information for reflow soldering of HVQFN48 package SOT619-1 Hx Gx D P 0.025 0.025 C (0.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 17. Abbreviations Table 36. Abbreviations Acronym Description AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General-Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter 18.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 19. Revision history Table 37. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC84X v.1.7 20180227 Product data sheet - LPC84X v.1.6 Modifications: LPC84X v.1.6 Modifications: LPC84X v.1.5 Modifications: • Updated Table 17 “Dynamic characteristic: FRO”: Max values: FRO clock frequency; Condition: 20 C  Tamb  70 C and FRO clock frequency; Condition: 40 C  Tamb  105 C.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 22. Contents 1 2 3 4 4.1 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.8 8.9 8.9.1 8.10 8.11 8.11.1 8.12 8.12.1 8.13 8.13.1 8.13.2 8.14 8.14.1 8.15 8.15.1 8.16 8.16.1 8.17 8.18 8.18.1 8.18.2 8.19 8.19.1 8.19.2 8.20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC84x NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12.3 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 WKTCLKIN pin (wake-up clock input) . . . . . . 12.5 SCTimer/PWM output timing . . . . . . . . . . . . . 12.6 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 USART interface. . . . . . . . . . . . . . . . . . . . . . . 12.9 Wake-up process . . . . . . . . . . . . . . . .