Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 99 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
11.14 USART interface
The actual USART bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for USART
master and slave synchronous mode is 10 Mbit/s.
[1] Based on simulated values. Not tested in production.
Table 37. USART dynamic characteristics
[1]
T
amb
= 40 C to 105 C; V
DD
= 1.8 V to 3.6 V; C
L
= 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter Conditions Min Typ Max Unit
USART master (in synchronous mode) 1.8 V  V
DD
 3.6 V
t
su(D)
data input set-up time 6 - - ns
t
h(D)
data input hold time 0 - - ns
t
v(Q)
data output valid time 5 - 11 ns
USART slave (in synchronous mode) 1.8 V  V
DD
 3.6 V
t
su(D)
data input set-up time 6 - - ns
t
h(D)
data input hold time 0 - - ns
t
v(Q)
data output valid time 9 - 25 ns
Fig 26. USART timing
Un_SCLK (CLKPOL = 0)
TXD
RXD
T
cy(clk)
t
su(D)
t
h(D)
t
v(Q)
START BIT0
t
vQ)
Un_SCLK (CLKPOL = 1)
START
BIT0
BIT1
BIT1
aaa-015074