Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 96 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
11.13 High-Speed SPI interface (Flexcomm Interface 10)
The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is <TBD> Mbit/s, and the maximum supported bit rate for SPI slave mode is <TBD>
Mbit/s.
[1] Based on simulated values. Not tested in production.
Table 36. SPI dynamic characteristics
[1]
T
amb
= 40 C to 105 C; V
DD
= 1.8 V to 3.6 V; C
L
= 10 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins;. Parameters sampled at the 50% level of the rising or falling edge.
Symbol Parameter Conditions Min Typ Max Unit
SPI master 1.8 V  V
DD
 3.6V
t
DS
data set-up time 4 - - ns
t
DH
data hold time 0 - - ns
t
v(Q)
data output valid time 3 - 8 ns
SPI slave 1.8 V  V
DD
 3.6V
t
DS
data set-up time 4 - - ns
t
DH
data hold time 0 - - ns
t
v(Q)
data output valid time 6 - 15 ns