Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 91 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
11.11 I
2
S-bus interface
[1] Based on simulation; not tested in production.
[2] Clock Divider register (DIV) = 0x0.
[3] Typical ratings are not guaranteed.
[4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section
in the I
2
S chapter (UM11126) to calculate clock and sample rates.
[5] Based on simulation. Not tested in production.
Table 34. Dynamic characteristics: I
2
S-bus interface pins
[1][4]
T
amb
= 40 C to 105 C; VBAT_DCDC = 1.8 V to 3.6 V; C
L
= 10 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW
setting = standard mode for all pins; Parameters sampled at the 50% level of the rising or falling edge.
Symbol Parameter Conditions Min Typ
[3]
Max Unit
Common to master and slave
t
WH
pulse width HIGH on pins I2Sx_TX_SCK and I2Sx_RX_SCK
[5]
(T
cyc
/2) -1 - (T
cyc
/2) +1 ns
t
WL
pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK
[5]
(T
cyc
/2) -1 - (T
cyc
/2) +1 ns
Master; 1.8 V  VDD  3.6 V
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
5 - 15 ns
on pin I2Sx_WS
5 - 12 ns
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
4-- ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[2]
0-- ns
Slave; 1.8 V  VDD  3.6 V
t
v(Q)
data output valid time on pin I2Sx_TX_SDA
[2]
9 - 26 ns
t
su(D)
data input set-up time on pin I2Sx_RX_SDA
[2]
4-- ns
on pin I2Sx_WS
4-- ns
t
h(D)
data input hold time on pin I2Sx_RX_SDA
[2]
0-- ns
on pin I2Sx_WS
0-- ns