Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 86 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
[1] Data based on characterization results, not tested in production.
[2] Output jitter depends on the frequency of input jitter and is equal to or less than the input jitter.
[3] Excluding under- and overshoot which may occur when the PLL is not in lock.
[4] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion
means lock output is HIGH.
[5] Actual jitter dependent on amplitude and spectrum of substrate noise.
[6] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.
Table 26. Dynamic characteristics of the PLL
[1]
Symbol Parameter Conditions Min Typ Max Unit
Reference clock input
f
ref
reference frequency input frequency at
PFD (clkref)
<tbd> - <tbd> -
f
ref-jitter
input jitter for
reference frequency
-
[2]
- - 10% of
period
frequency
-
Clock output
f
o
output frequency for PLL clkout
output
[3]
<tbd> - <tbd> MHz
d
o
output duty cycle for PLL clkout
output
<tbd> - <tbd> %
f
CCO
CCO frequency - - 550 MHz
Lock detector output

lock(PFD)
PFD lock criterion
[4]
<tbd> <tb
d>
<tbd> ns
Dynamic parameters at f
out
= f
CCO
= 100 MHz; standard bandwidth settings
J
rms-interval
RMS interval jitter f
ref
= 10 MHz
[5][6]
- <tb
d>
<tbd> ps
J
pp-period
peak-to-peak, period
jitter
f
ref
= 10 MHz
[5][6]
- <tb
d>
<tbd> ps