Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 85 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
11.4 PLL0
[1] Data based on characterization results, not tested in production.
[2] PLL set-up requires high-speed start-up and transition to normal mode. Lock times are only valid when
high-speed start-up settings are applied followed by normal mode settings. The procedure for setting up the
PLL is described in the <tbd> user manual.
[3] PLL current measured using lowest CCO frequency to obtain the desired output frequency.
Table 25. PLL0 lock times and current
T
amb
= 40 C to +105 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
PLL configuration: input frequency 12 MHz; output frequency 75 MHz
t
lock(PLL0)
PLL lock time PLL set-up procedure followed
[2]
<tbd> s
I
DD(PLL0)
PLL current when locked
[1][3]
- - <tbd> A
PLL configuration: input frequency 12 MHz; output frequency 100 MHz
t
lock(PLL0)
PLL lock time PLL set-up procedure followed
[2]
- - <tbd> s
I
DD(PLL0)
PLL current when locked
[1][3]
- - <tbd> A
PLL0 configuration: input frequency 32 kHz; output frequency 75 MHz
t
lock(PLL0)
PLL lock time -
[1]
<tbd> s
I
DD(PLL0)
PLL current when locked
[1][3]
- - <tbd> A
PLL0 configuration: input frequency 32 kHz; output frequency 100 MHz
t
lock(PLL0)
PLL lock time -
[1]
- - <tbd> s
I
DD(PLL0)
PLL current when locked
[1][3]
- - <tbd> A