Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 84 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
[1] Simulated data.
[2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between
80 % and 20 % of the full output signal level.
[3] The slew rate is configured in the IOCON block the SLEW bit. See the LPC55S6x user manual.
[4] C
L
= 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.
11.3 Wake-up process
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up
from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)
wake-up handler.
[3] FRO enabled, all peripherals off.
[4] RTC disabled. Wake-up from deep power-down causes the part to go through entire reset
process. The wake-up time measured is the time between when the RESET pin is triggered to wake the
device up and when a GPIO output pin is set in the reset handler.
Table 24. Dynamic characteristic: Typical wake-up times from low power modes
V
DD
= 3.3 V;T
amb
= 25 C; using FRO as the system clock.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
t
wake
wake-up
time
from Sleep mode
[2][3]
<tbd> s
from Deep-sleep mode with full
SRAM retention:
[2]
100 s
from Power-down mode with CPU
retention and 4 KB retained
[2]
325 s
from deep power-down mode; 4KB
retained, RTC disabled; using
RESET pin.
[4]
15 ms