Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 70 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
10.2 CoreMark data
[1] Clock source FRO. PLL disabled
[2] Characterized through bench measurements using typical samples.
[3] Compiler settings: IAR v.8.20.2, optimization level 3, optimized for time on.
[4] See the FLASHCFG register in the LPC55S6x User Manual for system clock flash access time settings.
Table 15. CoreMark score
T
amb
= 25C, VBAT_DCDC = 3.0 V
Parameter Conditions Typ Unit
ARM Cortex-M33 (CPU0) in active mode; ARM Cortex-M33 (CPU1) in sleep mode
CoreMark score CoreMark code executed from SRAMX;
CCLK = 12 MHz
[1][2][3]
3.8 (Iterations/s) / MHz
CCLK = 48 MHz
[1][2][3]
3.8 (Iterations/s) / MHz
CCLK = 96 MHz
[1][2][3]
3.8 (Iterations/s) / MHz
CoreMark score CoreMark code executed from flash;
CCLK = 12 MHz; 2 system clock flash
access time.
[1][2][3][4]
3.6 (Iterations/s) / MHz
CCLK = 48 MHz, 5 system clock flash
access time.
[1][2][3][4]
2.9 (Iterations/s) / MHz
CCLK = 96 MHz, 9 system clock flash
access time.
[1][2][3][4]
2.3 (Iterations/s) / MHz
Conditions: VBAT_DCDC = 3.0 V; T
amb
= 25 °C; active mode; See the FLASHCFG register in the
LPC55S6x, UM11126 User Manual for system clock flash access time settings. Measured with IAR
v.8.20.2. Optimization level 3, optimized for time on.
12 MHz (FRO, PLL disabled), 48 MHz (FRO, PLL disabled), 96MHz (FRO enabled; PLL disabled)
Fig 8. Typical CoreMark score <tbd>