Datasheet

Product data sheet Rev. 1.0 — 26 February 2019 64 of 123

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.30.2.1 Features

• Performs SHA-1 and SHA-2(256) based hashing.

• Used with HMAC to support a challenge/response or to validate a message.

7.30.3 PUF

The PUF controller on the LPC55S6x provides generation and secure storage for keys

without storing the key. The PUF controller provides a unique key per device and exists in

that device based on the unique characteristics of PUF SRAM. Instead of storing the key,

a Key Code is generated, which in combination with the digital fingerprint is used to

reconstruct keys that are routed to the AES engine, for use by software, and by PRINCE

engine. PUF keys have a dedicated path to the AES engine and PRINCE engine. There is

no other mechanism by which keys can be observed.

7.30.3.1 Features

• Key strength of 256-bits.

• The PUF constructs 256-bit strength device unique PUF root key using the digital

fingerprint of a device derived from SRAM and error correction data called Activation

Code (AC). The Activation Code (AC) is generated during enrollment process. The

Activation Code (AC) should be stored on external non-volatile memory device in the

system.

• Generation, storage, and reconstruction of keys.

• Key sizes from 64 bits to 4096 bits.

• PUF controller allows storage of keys, generated externally or on chip, of sizes 64 bits

to 4096 bits.

• PUF controller combines keys with digital fingerprint of device to generate key codes.

These key codes should be provided to the controller to reconstruct original key. They

can be stored on external non-volatile memory device in the system.

• Key output via dedicated hardware interface or through register interface.

• PUF controller allows to assign a 4-bit index value for each key while generating key

codes. Keys that are assigned index value zero are output through HW bus,

accessible to AES and PRINCE engines only. Keys with non-zero index are available

through APB register interface.

• 32-bit APB interface.

7.30.4 Random Number Generator

The True Random Number Generators (TRNG) module is a hardware accelerator module

that generate 256-bit entropy. The purpose of the module is to generate high quality,

cryptographically secure, random data.

Random number generators are used for data masking, cryptographic, modeling and

simulation application which employ keys that must be generated in a random fashion

LPC55S6x embeds a hardware IP that - combined with appropriate software and the

availability of a stochastic model - can be used to generate