Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 63 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
7.29.3 Temperature sensor
The temperature sensor transducer uses an intrinsic pn-junction diode reference and
outputs a Complement To Absolute Temperature (VC
TAT
) voltage. The output voltage
varies inversely with device temperature with an absolute accuracy of better than
<tbd> C over the full temperature range (<tbd> C to <tbd> C). The temperature sensor
is only approximately linear with a slight curvature. The output voltage is measured over
different ranges of temperatures and fit with linear-least-square lines.
After power-up, the temperature sensor output must be allowed to settle to its stable value
before it can be used as an accurate ADC input.
7.30 Security Features
The security system on LPC55S6xLPC55S6x has a set of hardware blocks and ROM
code to implement the security features of the device. The hardware consists of an AES
engine, a Secure Hash Algorithm (SHA) engine, a Random Number Generator (RNG), a
PRINCE engine for real-time flash encryption/decryption, and a key storage block that
keys from an SRAM based PUF (Physically Unclonable Function). All components of the
system can be accessed by the processor or the DMA engine to encrypt or decrypt data
and for hashing. The ROM is responsible for secure boot in addition to providing support
for various security functions.
7.30.1 AES engine
The LPC55S6xx devices provide an on-chip hardware AES encryption and decryption
engine to protect the image content and to accelerate processing for data encryption or
decryption, data integrity, and proof of origin. Data can be encrypted or decrypted by the
AES engine using a key from the PUF or a software supplied key. The AES engine
supports 128 bit, 192 bit, or 256 bit keys for encryption and decryption operations.
7.30.1.1 Features
• Encryption and decryption of data.
• Secure storage of AES key that cannot be read.
• Supports 128 bit, 192 bit or 256 bit key in Electronic Code Book (ECB) mode, Cipher
Block Chaining (CBC) mode, and Counter (CTR) mode.
• Supports 128-bit key in ICB (Indexed Code Book) mode, that offers protection against
side-channel attacks.
• Compliant with the FIPS (Federal Information Processing Standard) Publication 197,
Advanced Encryption Standard (AES).
• It may use the processor, DMA, or AHB Master for data movement. AHB Master may
only be used to load data, DMA may be used to read-out results. DMA based result
reading is a “trigger”, so the application must set the size correctly.
7.30.2 HASH engine
The LPC55S6x devices provide on-chip Hash support to perform SHA-1 and
SHA-2 with 256-bit digest (SHA-256). Hashing is a way to reduce arbitrarily large
messages or code images to a relatively small fixed size “unique” number called a digest.
The SHA-1 Hash produces a 160 bit digest (five words), and the SHA-256 hash produces
a 256 bit digest (eight words).