Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 59 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
RTC alarm and high-resolution/wake-up timer time-out each generate independent
interrupt requests that go to one NVIC channel. Either time-out can wake up the part
from any of the low power modes, including deep power-down.
Eight 32-bit general purpose registers can retain data in deep power-down or in the
event of a power failure, provided there is battery backup.
7.27.5 Multi-Rate Timer (MRT)
The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each
channel can be programmed with an independent time interval, and each channel
operates independently from the other channels.
7.27.5.1 Features
24-bit interrupt timer.
Four channels independently counting down from individually set values.
Repeat interrupt, one-shot interrupt, and one-shot bus stall modes.
7.27.6 OS Timer
42-bit free running timer with individual match/capture and interrupt generation logic used
as continuous time-base for the system, available in any reduced power modes. It runs on
32kHz clock source, allowing a count period of more than 4 years.
7.27.6.1 Features
Central 42-bit, free-running gray-code event/timestamp timer.
Match registers compared to the main counter to generate an interrupt and/or
wake-up event.
Capture registers triggered by CPU command, readable via the AHB/IPS bus.
APB interface for register access.
IRQ and wake-up.
Reads of gray-encoded timers are accomplished with no synchronization latency.
7.27.7 Micro-tick timer (UTICK)
The ultra-low power Micro-tick Timer, running from the Watchdog oscillator, can be used
to wake up the device from sleep and deep-sleep modes.
7.27.7.1 Features
Ultra simple timer.
Write once to start.
Interrupt or software polling.
Four capture registers that can be triggered by external pin transitions.