Datasheet
LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 55 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
7.25.4 High-speed SPI serial I/O controller
7.25.4.1 Features
• Master and slave operation.
• Maximum data rates of <tbd> Mbit/s at tbd V VDD tbd V in master and slave mode
for SPI functions.
• Data frames of 4 to 16 bits supported directly. Larger frames supported by software.
• The SPI function supports separate transmit and receive FIFOs with eight entries
each.
• Supports DMA transfers: SPIn transmit and receive functions can operated with the
system DMA controller.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
• Up to Four Slave Select input/outputs with selectable polarity and flexible usage.
7.26 SDIO/MMC interface
Secured digital input/output (SD/MMC and SDIO) card interface with DMA support. SDIO
with support for up to two cards. Supported card types are MMC, SDIO, and CE-ATA.
Supports SD2.0, and SDR25 (52MHz).
7.26.1 Features
• Secure Digital memory protocol commands.
• Secure Digital I/O protocol commands.
• Multimedia Card protocol commands.
• CE-ATA digital protocol commands.
• Two SD or MMC (4.4), CE-ATA (1.1), or eMMC (4.4) device.
• CRC 2.0 generation and error detection.
• SDIO interrupts in 1-bit and 4-bit modes.
• Block size of 1 to 65,535 bytes.
• Internal (bus mastering) DMA.
• Two FIFOs, TX and RX FIFO (FIFO depth = 32 and FIFO data width = 32 bits).
7.27 Standard counter/timers (CT32B0 to 4)
The LPC55S6x includes five general-purpose 32-bit timer/counters.
The timer/counter is designed to count cycles of the system derived clock or an
externally-supplied clock. It can optionally generate interrupts, generate timed DMA
requests, or perform other actions at specified timer values, based on four match
registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
7.27.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.