Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 54 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
• In synchronous slave mode, wakes up the part from deep-sleep and deep-sleep2
modes.
• Special operating mode allows operation at up to 9600 baud using the 32.768 kHz
RTC oscillator as the UART clock. This mode can be used while the device is in
deep-sleep and can wake-up the device when a character is received.
• USART transmit and receive functions work with the system DMA controller.
• The USART function supports separate transmit and receive FIFO with 16 entries
each.
7.25.3.5 I
2
S-bus interface
The I
2
S bus provides a standard communication interface for streaming data transfer
applications such as digital audio or data collection. The I
2
S bus specification defines a
3-wire serial bus with one data, one clock, and one word select/frame trigger signal,
providing single or dual (mono or stereo) audio data transfer in addition to other
configurations. Each Flexcomm Interface implements one I
2
S channel pair.
The I
2
S interface within one Flexcomm Interface provides one channel pair that can be
configured as a master or a slave. The channel pair within one Flexcomm Interface shares
one set of I
2
S signals, and are configured together for either transmit or receive operation,
using the same mode, same data configuration, and frame configuration. All such channel
pairs can participate in a Time Division Multiplexing (TDM) arrangement. For cases
requiring an MCLK input and/or output, this is handled outside of the I
2
S block in the
system level clocking scheme.
Features
• A Flexcomm Interface can implement one or more I
2
S channel pairs, the first of which
could be a master or a slave, and the rest would be slaves. All channel pairs are
configured together for either transmit or receive and other shared attributes.
• Flexcomm interfaces 0 to 7 each provide one channel pair of I
2
S function.
• Configurable data size for all channels within one Flexcomm Interface, from 4 bits to
32 bits. Each channel pair can also be configured independently to act as a single
channel (mono as opposed to stereo operation).
• All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and
word select/frame trigger (WS), and data line (SDA).
• Data for all I
2
S traffic within one Flexcomm Interface uses the Flexcomm FIFO. The
FIFO depth is 8 entries.
• Left justified and right justified data modes.
• DMA support using FIFO level triggering.
• TDM with a several stereo slots and/or mono slots is supported. Each channel pair
can act as any data slot. Multiple channel pairs can participate as different slots on
one TDM data line.
• The bit clock and WS can be selectively inverted.
• Sampling frequencies supported depends on the specific device configuration and
applications constraints (For example, system clock frequency and PLL availability)
but generally supports standard audio data rates.