Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 52 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
7.25.2.2 USB1 host controller
The host controller enables high speed data exchange with USB devices attached to the
bus. It consists of register interface and serial interface engine. The register interface
complies with the Enhanced Host Controller Interface (EHCI) specification
Features
• EHCI compliant.
• Two downstream ports.
• Supports per-port power switching.
7.25.3 Flexcomm Interface serial communication
Each Flexcomm Interface provides a choice of peripheral functions, one of which must be
chosen by the user before the function can be configured and used.
7.25.3.1 Features
• USART with asynchronous operation or synchronous master or slave operation.
• SPI master or slave with up to 4 slave selects.
• I
2
C, including separate master, slave, and monitor functions.
• Flexcomm interfaces 0 to 7 each provide one channel pair of I
2
S.
• Data for USART, SPI, and I2S traffic uses the Flexcomm FIFO. The I
2
C function does
not use the FIFO.
7.25.3.2 SPI serial I/O (SPIO) controller
Features
• Maximum data rates of <tbd> Mbit/s in master mode and <tbd> in slave mode for SPI
functions.
• Master and slave operation.
• Data frames of 4 to 16 bits supported directly. Larger frames supported by software.
• The SPI function supports separate transmit and receive FIFOs with eight entries
each.
• Supports DMA transfers: SPIn transmit and receive functions can operated with the
system DMA controller.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
• Up to Four Slave Select input/outputs with selectable polarity and flexible usage.
7.25.3.3 I
2
C-bus interface
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for exanple, an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and
can be controlled by more than one bus master connected to it.