Datasheet

Product data sheet Rev. 1.0 — 26 February 2019 48 of 123

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

7.22 Power control

The LPC55S6x support a variety of power control features. In Active mode, when the chip

is running, power and clocks to selected peripherals can be adjusted for power

consumption. In addition, there are four special modes of processor power reduction with

different peripherals running: sleep mode, deep-sleep mode, power-down mode, and

deep power-down mode which can be activated by the power mode configure API.

7.22.1 Sleep mode

In sleep mode, the system clock to both CPUs (CPU0 and CPU1) are stopped and

execution of instructions is suspended until either a reset or interrupt occurs. Peripheral

functions, if selected to be clocked can continue operation during sleep mode and may

generate interrupts to cause the processor to resume execution. Sleep mode eliminates

dynamic power used by the processor itself, memory systems and related controllers,

internal buses, and unused peripherals.

7.22.2 Deep-sleep mode

In deep-sleep mode, the flash is powered down. The system clock to both CPUs (CPU0

and CPU1) are stopped and if not configured, the peripherals receives no clocks. Through

the power profiles API, selected peripherals such as USB0, USB1, Flexcomm interfaces 0

to 7 (SPI, I2C, USART, I2S), Flexcomm interface 10 (High Speed SPI), Micro-tick, WWDT,

RTC, OSTimer, Standard Timers, comparator, and BOD can be left running in deep-sleep

mode. Clock sources such as FRO12 MHz, FRO 32 KHz, FRO 1 MHz, the 32.768 kHz

RTC clock, and the external oscillator can be enabled or disabled via software.

The LPC55S6x can wake up from deep-sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block and group interrupt block, OS Timer, Standard Timers,

Micro-tick, RTC alarm, a watchdog timer interrupt/reset, BOD interrupt/reset, an interrupt

from the USB0, USB1, SPI, I2C, I2S, USART, comparator, and PLU. Some peripherals

can have DMA service during deep-sleep mode without waking up entire device.

In deep-sleep mode, all SRAM, logic state, and registers maintain their internal states. All

SRAM instances that are not configured to enter in ‘retention state’ will stay in active state.

Deep-sleep mode allows for very low quiescent power and fast wake-up options.

7.22.3 Power-down mode

In power-down mode, nearly all on-chip power consumption is turned off by shutting down

the internal DC-DC converter. The flash is powered down. The system clock to both CPUs

(CPU0 and CPU1) are stopped and if not configured, the peripherals receives no clocks.

Through the power profiles API, selected peripherals such as Flexcomm interfaces 3 (SPI,

I2C, USART, I2S), RTC, OS Timer, and comparator can be left running in power-down

mode. Clock sources such as FRO 32 KHz, and the 32.768 kHz RTC clock can be

enabled or disabled via software.

The LPC55S6x can wake up from power-down mode via a reset, digital pins selected as

inputs to the group interrupt block, OS Timer, RTC alarm, an interrupt from the Flexcomm

Interface 3 (SPI, I2C, I2S, USART), and comparator.

In power-down mode, the CPU0 processor state can be retained to allow resumption of

code execution when a wake-up event occurs.