Datasheet

Product data sheet Rev. 1.0 — 26 February 2019 45 of 123

NXP Semiconductors

LPC55S6x

32-bit ARM Cortex-M33 microcontroller

entire voltage and temperature range. The FRO 12 MHz oscillator provides the

default clock at reset and provides a clean system clock shortly after the supply pins

reach operating voltage.

• 32 kHz Internal Free Running Oscillator FRO. The FRO is trimmed to +/- 65%

accuracy over the entire voltage and temperature range.

Internal low power oscillator (FRO 1 MHz). The FRO is trimmed to +/- 15% accuracy

over the entire voltage and temperature range.

• Crystal oscillator with an operating frequency of 1 MHz to 25 MHz. Option for external

clock input (bypass mode) for clock frequencies of up to 25 MHz

• Crystal oscillator with 32.768 KHz operating frequency.

7.21.2 PLL (PLL0 and PLL1)

PLL0 and PLL1 allows CPU operation up to the maximum CPU rate without the need for a

high-frequency external clock. PLL0 and PLL1 can run from the internal FRO 12 MHz

output, the external oscillator, internal FRO 1 MHz output, or the 32.768 KHz RTC

oscillator.

The system PLL accepts an input clock frequency in the range of 2 kHz - 150 MHz (max

limited to 100 MHz). The input frequency is multiplied up to a high frequency with a

Current Controlled Oscillator (CCO). The PLL can be enabled or disabled by software.

7.21.3 Clock generation

The system control block facilitates the clock generation. Many clocking variations are

possible. Figure 5 gives an overview of potential clock options. Table 10 describes signals

on the clocking diagram. The maximum clock frequency is 100 MHz.

Remark: The indicated clock multiplexers shown in Figure 5 are synchronized. In order to

operate, the currently selected clock must be running, and the clock to be switched to

must also be running. This is so that the multiplexer can gracefully switch between the two

clocks without glitches. Other clock multiplexers are not synchronized. The output divider

can be stopped and restarted gracefully during switching if a glitch-free output is needed.

The low-power oscillator provides a frequency in the range of 1 MHz. The accuracy of this

clock is limited to +/- 10% over temperature, voltage, and silicon processing variations

after trimming made during assembly. To determine the actual watchdog oscillator output,

use the frequency measure block.

The part contains one system PLL that can be configured to use a number of clock inputs

and produce an output clock in the range of 1.2 MHz up to the maximum chip frequency,

and can be used to run most on-chip functions. The output of the PLL can be monitored

through the CLKOUT pin.

Table 10. Clocking diagram signal name descriptions

Name Description

32k_osc The 32 kHz output of the RTC oscillator. The 32 kHz clock must be enabled in the RTCOSCCTRL register.

clk_in This is the internal clock that comes from the external oscillator.

frg_clk The output of each Fractional Rate Generator to Flexcomm clock. Each FRG and its source selection is shown in

Figure 5.

fro_12m 12 MHz divided down from the currently selected on-chip FRO oscillator.

fro_hf The currently selected FRO high speed output at 96 MHz.