Datasheet

LPC55S6x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2019. All rights reserved.
Product data sheet Rev. 1.0 — 26 February 2019 42 of 123
NXP Semiconductors
LPC55S6x
32-bit ARM Cortex-M33 microcontroller
[1] The size shown for peripherals spaces indicates the space allocated in the memory map, not the actual
space used by the peripheral or memory.
[2] Selected areas of secure regions may be marked as non-secure callable. See <tbd>.
7.17 Links to specific memory map descriptions and tables:
• Section 7.18 “Memory map overview”
• Section 7.19 “APB peripherals”
• Section 7.20 “AHB peripherals”
7.18 Memory map overview
Table 7 gives a more detailed memory map as seen by the Cortex-M33. The purpose of
the four address spaces for the shared RAMs is outlined at the beginning of this chapter.
The details of which shared RAM regions are on which AHB matrix slave ports can be
seen here.
[1] Gaps between AHB matrix slave ports are not shown.
Table 7. Memory map overview
AHB
port
Non-secure
start address
Non-secure
end address
Secure start
address
Secure end
address
Function
[1]
0 0x0000 0000 0x0009 FFFF 0x1000 0000 0x1009 FFFF Flash memory, on CM33 code bus. The last 20 pages
(10 KB) are reserved.
0x0300 0000 0x0301 FFFF 0x1300 0000 0x1301 FFFF Boot ROM, on CM33 code bus.
1 0x0400 0000 0x0400 7FFF 0x1400 0000 0x1400 7FFF SRAM X on CM33 code bus, 32 KB. SRAMX_0
(0x1400 0000 to 0x1400 0FFF) and SRAMX_1
(0x1400 4000 to 0x1400 4FFF) are used for Casper
(total 8 KB). If CPU retention used in power-down
mode, RAMX_3 (0x1400 7000 to 0x1400 73FF) is
used (total 1 KB) by default in power API and this is
user configurable within RAMX_2 and RAMX_3.
2 0x2000 0000 0x2000 FFFF 0x3000 0000 0x3000 FFFF RAM 0 on CM33 data bus, 64 KB.
3 0x2001 0000 0x2001 FFFF 0x3001 0000 0x3001 FFFF RAM 1 on CM33 data bus, 64 KB.
4 0x2002 0000 0x2002 FFFF 0x3002 0000 0x3002 FFFF RAM 2 on CM33 data bus, 64 KB.
5 0x2003 0000 0x2003 FFFF 0x3003 0000 0x3003 FFFF RAM 3 on CM33 data bus, 64 KB.
6 0x2004 0000 0x2004 3FFF 0x3004 0000 0x3004 3FFF RAM 4 on CM33 data bus, 16 KB. SRAM4_0 (0x3004
0000 to 0x3004 0FFF), SRAM4_1 (0x3004 1000 to
0x3004 1FFF), SRAM4_2 (0x3004 2000 to 0x3004
2FFF), and SRAM4_3 (0x3004 3000 to 0x3004 3FFF)
are used for PowerQuad (total 16 KB).
7 0x4000 0000 0x4001 FFFF 0x5000 0000 0x5001 FFFF AHB to APB bridge 0. See
Section 7.19.
0x4002 0000 0x4003 FFFF 0x5002 0000 0x5003 FFFF AHB to APB bridge 1. See
Section 7.19.
8 0x4008 0000 0x4008 FFFF 0x5008 0000 0x5008 FFFF AHB peripherals. See
Section 7.20.
9 0x4009 0000 0x4009 FFFF 0x5009 0000 0x5009 FFFF AHB peripherals. See
Section 7.20.
10 0x400A 0000 0x400A FFFF 0x500A 0000 0x500A FFFF AHB peripherals. See
Section 7.20.
11 0x4010 0000 0x4010 FFFF 0x5010 0000 0x5010 FFFF AHB peripherals. See
Section 7.20.